En raison d’un problème dans les versions logicielles 16.1.2 et antérieures de Quartus Prime® votre Arria® 10 SerialLite™ III peut présenter des violations de la synchronisation de configuration dans les chemins entre le nœudpld_10g_tx_pempty_reg» et le «altera standard synchronizer stdsync_txpempty|din_s1» du type ci-dessous :
De nœud : seriallite_iii_streaming:seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa:seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:DUPLEX_WRAPPER.interlaken_inst|seriallite_iii_streaming_altera_xcvr_native_a10_161_koe2tsa : native_ilk_wrapper|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg
Au nœud : seriallite_iii_streaming:seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa:seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[5].stdsync_txpempty|din_s1
Horloge de lancement : seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[*]|tx_pma_clk
Horloge de loquet : seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[0]|tx_pma_clk
Pour contourner ce problème, l’utilisateur doit modifier le fichier ip .sdc généré(seriallite_iii_streaming*.sdc).
Les contraintes originales de .sdc se trouvent ci-dessous :
set_max_skew -de [get_keepers{*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] à [get_keepers {*$module_name*|interlaken_native_wrapper_duplex|stdsync_txpempty|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0,85
set_net_delay :de [get_keepers{*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.. inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -à [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*: A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0,85
set_max_delay : de [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] à [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_* : A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] 100
set_min_delay de [get_keepers{*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -à [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*: A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] -100
Doit être remplacé par les contraintes suivantes :
définir inst_xcvr_list [get_entity_instances twentynm_xcvr_native]
each_xcvr_inst foreach \$inst_xcvr_list {
si {[chaîne égale « quartus_sta » \$::TimeQuestInfo (nameofexeable)] } {
set_max_skew -de [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] à [get_keepers {*stdsync_txpempty|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0,85
}
set_net_delay -de [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] à [get_keepers {*stdsync_txpempty|din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0,85
set_max_delay -de [get_keepers\$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] à [get_keepers {*stdsync_txpempty|din_s1}] 100
set_min_delay -de [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] à [get_keepers {*stdsync_txpempty|din_s1}] -100
}
Ce problème a été résolu à partir de la version 17.0 du logiciel Quartus Prime®.