Intel® High Level Synthesis Compiler


The Intel® HLS Compiler is a high-level synthesis (HLS) tool that takes in untimed C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel® FPGAs. This tool accelerates verification time over RTL by raising the abstraction level for FPGA hardware design. Models developed in C++ are typically verified orders of magnitude faster than RTL.

Intel® HLS Compiler is included in the Intel® Quartus® Prime Design Software installation.

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Intel® HLS Compiler Success Story

Horizon Robotics is partnering with Intel to develop embedded AI applications. Learn how Horizon Robotics is using the Intel® Arria® 10 FPGA and Intel® HLS Compiler to do real-time pixel level segmentation for 3D semantic modeling and localization.


The Intel® HLS Compiler for Intel® Quartus® Prime Design Software provides various capabilities to enable hardware programmers to use C++ for accelerating their FPGA development process.

  • Uses untimed ANSI C++ as the golden design source
  • Allows you to quickly explore multiple architectures through high-level directives
  • Simplifies tool usage by inferring design intent from high-level constraints
  • Supports verification of RTL by comparison with the original C++ source model
  • Generates reusable intellectual property (IP) for system integration using the Platform Designer (formerly Qsys)
  • Supports inference of streaming, memory mapped, or wire interfaces
  • Performs device-specific timing-driven schedule optimization and technology mapping for Intel® FPGAs
  • Supports a software compiler use model and industry standards including ac_int data types
  • Detailed reporting feature for a birds-eye view: High-level design HTML reports are automatically generated during the simulation stage lets users see bottlenecks in their design
  • Allows users to view and analyze: Area utilization, loop structure, memory usage, system data flow, clusters, and surrounding logic
  • Supports multiple flows to integrate IP in a system. Integrate HLS code through direct HLD instantiation, through Platform Designer, or onto an Intel® Programmable Acceleration Card (Intel® PAC)

What's New in 20.3

An Intuitive Design Environment

  • New Loop Visualization GUI (Beta) and Bottleneck Viewer enables deeper insights for easier optimization
  • Pipes can connect HLS components to testbenches

Area or Performance Improvements

  • Loops with different trip counts can be fused using pragma or automatically
  • Streams & channels in Intel® Stratix® 10 & Intel® Agilex™ device families can lower FIFO usage (less FIFO usage) by enabling Hyperflex optimized handshaking
  • Pipes enable fast, intra FPGA, connections between tasks. Also, create array of pipes

Getting Started

Documentation and Support

Find technical documentation, videos, and training courses for Intel® HLS Compiler.