DSP Builder for Intel® FPGAs is a digital signal processing (DSP) design tool that allows push-button HDL generation of DSP algorithms directly from the MathWorks Simulink* environment on Intel® FPGAs. The tool generates high quality, synthesizable VHDL/Verilog code from MATLAB functions, and Simulink models. The generated RTL code can be used for Intel® FPGA programming. DSP Builder for Intel® FPGAs is widely used in radar designs, wireless and wireline communication designs, medical imaging, and motor control applications.
DSP Builder for Intel® FPGAs adds additional library blocks alongside existing Simulink libraries with DSP Builder for Intel® FPGAs (Advanced Blockset) and DSP Builder for Intel® FPGAs (Standard Blockset). Our recommendation is to use DSP Builder for Intel® FPGAs (Advanced Blockset) for new designs.
To evaluate Intel® FPGAs for a model-based design flow, you will need a license for DSP Builder for Intel® FPGAs, the Intel® Quartus® Prime Design Software, MathWorks MATLAB/Simulink*, and MathWorks Fixed-Point Designer (sold separately). Request for a 30-day trial of MATLAB and Simulink products for use with DSP Builder for Intel® FPGAs.
DSP Builder for Intel® FPGAs enables the implementation of DSP designs with high performance and productivity benefits. Here are some highlighted features:
- Import RTL into your MathWorks* MATLAB/Simulink environment for co-simulation and code generation
- Go from high-level schematic to low-level optimized VHDL targeted for Intel® FPGAs
- Perform high-performance fixed- and floating-point digital signal processing (DSP) with vector processing, such as complex IEEE 754 single-precision floating point
- Perform push-button design migration to Intel's hard floating-point DSP block in Intel® Arria® 10 and Intel® Stratix® 10 devices
- Build custom arithmetic logic unit (ALU) processor architectures from a flat data-rate design with ALU folding
- Perform high-level synthesis optimizations, auto-pipeline insertion and balancing, and targeted hardware mapping
- Build custom fast Fourier transform (FFT) algorithms using a flexible ‘white-box’ fast Fourier transform (FFT) toolkit with an open hierarchy of libraries and blocks
- Use a designer-specified system clock constraint to automatically pipeline, time-division multiplex/fold, and close timing
- Access advanced math.h functions and multichannel data
- Generate resource utilization tables for all designs without a Intel® Quartus® Prime Software compile
- Automatically generate projects or scripts for the Intel® Quartus® Prime Software, Timing Analyzer, Platform Designer (formerly Qsys), and ModelSim*-Intel® FPGA Edition