Risk Factors

•Today’s presentations contain forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. Please refer to our most recent Earnings Release and our most recent Form 10-Q or 10-K filing for more information on the risk factors that could cause actual results to ...differ. •If we use any non-GAAP financial measures during the presentations, you will find on our website, intc.com, the required reconciliation to the most directly comparable GAAP financial measure. Rev. 4/19/11 Today’s News The world’s first 3-D Tri-Gate transistors on a production technology New 22nm transistors have an unprecedented combination of power savings and performance gains. These benefits will enable new innovations across a broad range of devices from the smallest handheld devices to powerful cloud-based servers. The transition to 3-D transistors continues the pace of technology advancement, fueling Moore’s Law for years to come. The world’s first demonstration of a 22nm microprocessor -- code-named Ivy Bridge -- that will be the first high-volume chip to use 3-D Tri-Gate transistors. Energy-Efficient Performance Built on Moore’s Law 1 65nm 45nm 32nm 22nm 1x (normalized) Leakage Power Transistor Transistor 0.1x Active per Lower > Lower50% 0.01x Power reduction Active 0.001x Constant Performance 0.1 65nm 45nm 32nm 22nm Higher Transistor Performance (Switching Speed) Planar Planar Planar Tri-Gate Source: Intel 22 nm Tri-Gate transistors increase the benefit from a new technology generation Source: Intel Transistor Innovations Enable Technology Cadence 2003 90 nm 2005 65 nm 2007 45 nm 2009 32 nm 2011 22 nm Invented SiGe Strained Silicon Strained Silicon nd 2 Gen. SiGe Strained Silicon Invented Gate-Last High-k Metal Gate nd 2 Gen. Gate-Last High-k Metal Gate First to Implement Tri-Gate High k Metal gate Tri-Gate Transistor Innovations Enable Cost Benefits of Moore’s Law to Continue 1 0.1 $ / Transistor (relative to 0.35um) 0.01 200mm 300mm Source: Intel 0.001 .35um .25um .18um .13um 90nm 65nm 45nm 32nm 22nm 14nm 10nm 22 nm Manufacturing Fabs D1D -- Oregon D1C -- Oregon Fab 32 -- Arizona Fab 28 -- Israel Fab 12 -- Arizona 22nm upgrades to be completed 2011-12 Tri-Gate Invented Tri-Gate Achievement Results from Long Term Commitment to Research Pathfinding Internal Research Development Tri-Gate Selected for 22nm node CE! transfer Manufacturing Tri-Gate Mfg Single-fin transistor demonstrated Multi-fin transistor demonstrated Tri-gate SRAM cells demonstrated Tri-gate RMG process flow developed Tri-gate optimized for HVM Bringing innovative technologies to HVM is the result of a highly coordinated internal research-development-manufacturing pipeline “For years we have seen limits to how small transistors can get,” said Gordon E. Moore. “This change in the basic structure is a truly revolutionary approach, and one that should allow Moore’s Law, and the historic pace of innovation, to continue.” 22 nm 3-D Tri-Gate Transistor Source: Intel 3-D Tri-Gate transistors form conducting channels on three sides of a vertical fin structure, providing “fully depleted” operation Transistors have now entered the third dimension! 22 nm 3-D Tri-Gate Transistor Source: Intel Gates Fins 32 nm Planar Transistors 22 nm Tri-Gate Transistors Source: Intel Std vs. Fully Depleted Read the full Risk Factors.