ID:16100 IBIS model for pin "<name>" at package pin <name> is not available

CAUSE: You directed the Compiler to generate an IBIS Output File (.ibs) for performing board-level signal integrity verification of Intel FPGA devices with other EDA tools, specified that the minimum or maximum RLC (resistance, inductance, and capacitance) IBIS model values be used for the I/O, dedicated input, VCC, GND, and global clock pins in the IBIS Output File, and then compiled the project. However, the appropriate IBIS model for the specified pin in the top-level design file, that corresponds to the specified pin in the device package, is not available.

ACTION: For the latest IBIS models, go to the IBIS Models for Intel FPGA Devices section of the Intel FPGA web site.