ID:19651 Verilog HDL warning at <location>: latch inferred for net <string>

CAUSE: In a Design File at the specified location, Quartus inferred a latch. Inferred latches are often unintended in FPGA designs.This may happen when one or more variables are not assigned to in all branches of conditionals or case statements, such as the following example where y is not set in all cases of the case statement:

always@(*)
begin
  case (sel)
    1'b0: begin
      x = d1;
      y = d2;
    end

               
    1'b1: begin
      x = d3;
    end
    default: begin
      x = d3;
    end
  endcase
end

            

This situation can also occur when a case statement is missing a default case.Quartus may also infer a latch when feedback loops are present in combinational logic, such as in the following example:

wire s;
assign s = in1 ? s : in2;