ID:24291 For LVDS SERDES design, review "Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank" as outlined in the Intel Agilex 7 General-Purpose I/O User Guide:M-Series.

CAUSE: The design violates Intel Agilex 7 placement restriction on LVDS and LVCMOS I/O standards.

ACTION: Review the Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank in the Intel Agilex 7 General-Purpose I/O User Guide:M-Series and add pin location assignment.