dmardlr

Controls DMA Receive FIFO Threshold

Module Instance	Base Address	Register Address
`spis0`	`0xFFE02000`	`0xFFE02054`
`spis1`	`0xFFE03000`	`0xFFE03054`

Offset: 0x54

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`dmardl` `RW 0x0`

dmardlr Fields

Bit	Name	Description	Access	Reset
7:0	`dmardl`	This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or above this field value + 1, and RDMAE=1.	`RW`	`0x0`