idinten

Various DMA Interrupt Enable Status
Module Instance Base Address Register Address
sdmmc 0xFF704000 0xFF704090

Offset: 0x90

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ai

RW 0x0

ni

RW 0x0

Reserved

ces

RW 0x0

du

RW 0x0

Reserved

fbe

RW 0x0

ri

RW 0x0

ti

RW 0x0

idinten Fields

Bit Name Description Access Reset
9 ai

This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt

Value Description
0x1 Abnormal Interrupt Summary is enabled
0x0 Abnormal Interrupt Summary is disabled
RW 0x0
8 ni

Enable and Disable Normal Interrupt Summary

Value Description
0x1 Normal Interrupt Summary is enabled
0x0 Normal Interrupt Summary is disabled
RW 0x0
5 ces

Enable and disable Card Error Interrupt Summary

Value Description
0x1 Card Error Summary Interrupt is enabled
0x0 Card Error Summary Interrupt is disabled
RW 0x0
4 du

When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled.

Value Description
0x1 Descriptor Unavailable Interrupt is enabled
0x0 Descriptor Unavailable Interrupt is disabled
RW 0x0
2 fbe

When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled.

Value Description
0x1 Fatal Bus Error Interrupt is enabled
0x0 Fatal Bus Error Interrupt is disabled
RW 0x0
1 ri

Enables and Disables Receive Interrupt when Normal Interrupt Summary Enable is set.

Value Description
0x1 Receive Interrupt is enabled
0x0 Receive Interrupt is disabled
RW 0x0
0 ti

Enables and Disables Transmit Interrupt when Normal Interrupt Summary Enable is set.

Value Description
0x1 Transmit Interrupt is enabled
0x0 Transmit Interrupt is disabled
RW 0x0