functional defects or errors, which may cause the product to deviate from published
specifications. Documentation issues include errors, unclear descriptions, or
omissions from current published specifications or product documents.
information on errata and the versions affected by errata, refer to the Knowledge Base
page of the
1.2. DSP Builder for Intel FPGAs Advanced Blockset Revision History
Table 1. Revision History
Added Finite State Machine block and design example.
Added support for MATLAB version: R2020b
Removed device selector in Device Parameters panel.
Added support for Intel Agilex® devices.
Added support for two new floating-point types float16_m7 (bfloat) and float19_m10.
Added dependent latency feature.
Added FIFO buffer fill-level reporting.
Added HDL import.
Added C++ software models.
Added support for automatic reset minimization of DSP Builder designs. Reset minimization determines the minimal set of registers in a design that require reset, while retaining the design’s correct functionality. Reducing the number of registers that DSP Builder resets may give improved quality of results i.e. reduced area and increased Fmax.
Added support for bit fields to the SharedMem block. These fields provide analogous functionality to the existing bit field support in the RegField and RegOut blocks.
Added beta support for HDL import, which incorporates VHDL or Verilog HDL synthesizable designs into a DSP Builder design. You can then cosimulate the imported design with DSP Builder Simulink components. HDL import includes a minimal user interface, but requires some manual setup. To use this feature, you require a license for the MathWorks HDL Verifier tool.
Added super-sample NCO design example.
Added support for
Cyclone® 10 and
Stratix® 10 devices.
Removed instances of Signals block.
Deleted WYSIWYG option on SynthesisInfo block.
Rebranded as Intel
Deprecated Signals block
Added Gaussian and Random Number Generator design examples
Added variable-size supersampled FFT design example
Added HybridVFFT block
Added GeneralVTwiddle and GeneralMultVTwiddle blocks
Added 4-channel 2-antenna DUC and DDC for LTE reference design
Added BFU_simple block
Created Standard and Pro editions. Pro supports Arria 10 devices; Standard supports all other families.
Deprecated the Signals block
Added functionality for setting the Avalon-MM interface settings in the DSP Builder menu
Improved folding results on MAX 10 devices
Added new design examples:
Gaussian Random Number Generator
DUC_4C4T4R and DDC_4C4T4R LTE digital-up and down-conversion
Added new FFT pruning strategy: prune_to_widths()
Deprecated Run Quartus II and Run Modelsim blocks
Added clock crossing support
Added reconfigurable FIR filters
Improved bus interfaces:
Improved error checking and reporting
Improved simulation accuracy
Improved bus slave logic implementation
Improved clock crossing
Changed some Avalon-MM interfaces
Added new blocks:
Added IIR: full-rate fixed-point and IIR: full-rate floating-point demos
Added transmit and receive modem reference design
Added support for SystemVerilog output
Added external memories library
Added External Memory block
Added new Allow write on both ports parameter to DualMem block
Changed parameters on AvalonMMSlaveSettings block
Added support for Arria 10 hard-floating-point blocks
Added BusStimulus and BusStimulusFileReader blocks to memory-mapped registers design example.
Added AvalonMMSlaveSettings block and DSP Builder > Avalon Interfaces > Avalon-MM slave menu option
Removed bus parameters from Control and Signal blocks
Removed the following design examples:
Color Space Converter (Resource Sharing Folding)
Interpolating FIR Filter with Updating Coefficients
DSP Builder for Intel® FPGAs integrates with MathWorks
MATLAB and Simulink tools and with the
Ensure at least one version of The MathWorks MATLAB and Simulink tool is
available on your workstation before you install DSP Builder for Intel® FPGAs. You should use the same version of the
Quartus® Prime software and DSP Builder for Intel® FPGAs. DSP Builder for Intel® FPGAs only
supports 64-bit versions of MATLAB.
From v18.0, DSP Builder for Intel® FPGAs advanced blockset is
Quartus® Prime Pro Edition and
Quartus® Prime Standard Edition. DSP Builder for Intel® FPGAs standard blockset is only available for
Quartus® Prime Standard Edition.
Table 2. DSP Builder for Intel® FPGAs MATLAB
MATLAB Supported Versions
DSP Builder Standard Blockset
DSP Builder Advanced Blockset
Quartus® Prime Standard Edition
Quartus® Prime Pro Edition
Note: The DSP Builder for Intel® FPGAs advanced blockset uses Simulink fixed-point types for all
operations and requires licensed versions of Simulink Fixed Point. Intel also recommends the DSP System Toolbox
and the Communications System Toolbox, which some design examples use.