Intel® Stratix® 10 DX FPGAs and SoCs enable next generation high bandwidth applications ranging from cache-coherent accelerators, custom servers for Cloud Service Providers (CSPs), and higher performance SmartNICs. They are the first FPGA devices to support Intel® Ultra Path Interconnect (Intel® UPI) for direct coherent connection to future select Intel® Xeon® Scalable processors. It also includes PCIe* Gen4 x16 interface at 16Gbps for faster connectivity.
Coherent Connection to future select Intel® Xeon® Scalable processors and Faster Connectivity through PCIExpress* hard and soft intellectual property (IP) blocks in supports up to Gen4 x16 at 16Gbps per lane with port bifurcation: 2x8 endpoint or 4x4 rootport modes.
Intel® Ultra Path Interconnect (Intel® UPI) hard IP with up to 20 lanes at 11.2Gbps for direct cache coherent connection to future select Intel® Xeon® Scalable processors.
Intel® Stratix® 10 DX device variants come with up to 8GB of integrated High Bandwidth Memory 2 (HBM2) DRAM at 512GBps bandwidth or a 64 bit quad-core Arm* Cortex-A53 Hard Processor Subsystem.
Intel® Stratix® 10 DX devices deliver Dual Mode modulation, 57.8 Gbps PAM 4 and 28.3 Gbps NRZ enabling early adoption of next generation data infrastructure and backward-compatibility with existing infrastructure in Network Functions Virtualization, Cloud Computing, and 5G Wireless industries.
Introducing Intel® Stratix® 10 DX FPGA for your high bandwidth and evolving data center requirements. It is the first FPGA to support Intel® Ultra Path Interconnect (UPI), PCIe Gen4 x16 and select Intel® Optane™ DC Persistent Memory DIMMs. Watch this video to learn more!
Intel® Enpirion® Power Solutions are high-frequency DC-DC step-down power converters designed and validated for Intel® FPGA, CPLD, and SoCs. These robust, easy-to-use power modules integrate nearly all of the components needed to build a power supply – saving you board space and simplifying the design process.
Comparison based on Stratix® V vs. Intel® Stratix® 10 using Intel® Quartus® Prime Pro 16.1 Early Beta. Stratix® V Designs were optimized using 3 step optimization process of Hyper-Retiming, Hyper-Pipelining, and Hyper-Optimization in order to utilize Intel® Stratix® 10 architecture enhancements of distributed registers in core fabric. Designs were analyzed using Intel® Quartus® Prime Pro Fast Forward Compile performance exploration tool. For more details, refer to Intel® Hyperflex™ FPGA Architecture Overview White Paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf. Actual performance users will achieve varies based on level of design optimization applied. Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.fr/benchmarks.