Intel® Arria® 10 FPGAs deliver more than a speed grade faster core performance and up to a 20% fMAX advantage compared to the competition, using publicly-available OpenCore designs.1 Intel® Arria® 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry’s only hard floating-point digital signal processing (DSP) blocks with speeds up to 1.5 tera floating-point operations per second (TFLOPS).1
The Intel® Arria® 10 FPGAs and SoCs are ideal for a broad array of applications such as communications, data center, military, broadcast, automotive, and other end markets.
Industry’s Only 20 nm ARM-Based SoC
Save Board Space with Integration
Increase Productivity and Decrease Time to Market with the Intel Quartus® Prime Software
Get ahead and get started with your Intel® Arria® 10 device design today. Reap the benefits of higher performance, lower power, and faster time to market that Intel® Arria® 10 devices offer.
The new revolutionary Intel® Quartus® Prime design software includes everything you need to design for Intel FPGAs, SoCs, and CPLDs from design entry and synthesis to optimization, verification, and simulation. Dramatically increased capabilities on devices with multi-million logic elements, are providing designers with the ideal platform to meet next-generation design opportunities. For designers to effectively take advantage of these devices, software must dramatically increase design productivity. The new Intel® Quartus® Prime software, built on the successful Quartus® II software, is breaking barriers of FPGA design productivity.
The Intel® Quartus® Prime design software enables new levels of design productivity for next-generation programmable devices with a set of faster and more scalable algorithms, a hierarchical database infrastructure, and a unified compiler technology. The Intel® Quartus® Prime software further extends the software leadership by delivering:
The Interface Planner allows you to explore a device’s peripheral architecture and efficiently assign interfaces. The Interface Planner prevents illegal pin assignments by performing fitter and legal checks in real time, eliminating complex error messages and the need to wait for a full compile, speeding up your I/O design by 10X.1
We are now shipping Intel® Arria® 10 FPGA development kits that help you:
Multiple design examples and reference designs are available for Intel® Arria® 10 FPGA kits.
For a list of all Intel® Arria® 10 FPGA designs.
Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.fr/benchmarks.
OpenCL™ and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.