Intel® Intelligent Fabric Processors
Enhance Ethernet switching with intelligence, high-performance, and edge-to-cloud telemetry for visibility and manageability.
Intel® Intelligent Fabric Processors
Accelerate Network Performance
Service providers and enterprises require smarter networks to keep up with accelerated data growth and the rise of demanding distributed workloads. Intel® Intelligent Fabric Processors (Intel® IFPs) enhance Ethernet switching with intelligence, high-performance, and real-time edge-to-cloud telemetry for visibility and manageability. Driven by P4-programmability, machine learning (ML) workload acceleration, and highly secure solutions, Intel® IFPs accelerate packet processing for edge and cloud data centers, high performance computing (HPC), and communications service providers.
Cloud-to-Edge Programmable Networks
The roles of programmability, automation, and intelligence in networks is driving a digital transformation across industries. Ed Doe, VP and general manager of Intel’s Switch and Fabric Group, discusses how Intel is helping businesses migrate to programmable networks in his presentation at Intel® Vision. We’re enabling and promoting open software specifications with our broad portfolio through Intel® Intelligent Fabric architecture.
Intel® Intelligent Fabric Use Cases
Transform network and business needs with Intel® Intelligent Fabric. Cloud service providers, communication service providers, and high-performance computing/AI users benefit from improved network performance, intelligence, visibility, and control. Additional use cases include real-time network telemetry, load balancing, and in-network DDoS detection.
Intel® Connectivity Education Hub
Learn how the P4 programming language can transform your network infrastructure end to end. Browse academic courses, subscribe to advanced online videos, or join our research program. The education hub gives you the resources and skills to develop powerful and efficient networking solutions with our connectivity products.
FAQ
Foire aux questions
No. ASIC cost is determined by die size. The Intel® Tofino™ die size is similar to the die of legacy fixed-function ASICs running at the same speed.
No. In fact, in many cases they consume less. For equivalent features and protocols, the power consumption is identical. In a programmable switch, you can turn off features you don’t need and reduce power or use smaller tables.
No. With Intel® Tofino™ and Intel® Tofino™ 2, we have shown that programmability does not come with a compromise on performance. Intel® Tofino™ and Intel® Tofino™ 2 can be fully programmed by users, using the P4 programming language, and can currently process up to 12.8 Tb/s.
P4 is an Apache-licensed open source language owned by P4.org, an independent nonprofit. Any company, university, or individual can join P4.org free and contribute to the language, compiler, and tools. Intel is one of over 100 members of P4.org, including companies from all across our industry, from AT&T to ZTE, and some of the world’s top universities. The P4.org Advisory Board consists of Amin Vahdat (Google), Jennifer Rexford (Princeton), Nate Foster (Cornell), Guru Parulkar (ONF), and Nick McKeown (Stanford/Intel). The language was designed by world experts in programming language design from Princeton, Cornell, Stanford, VMware, Intel, Microsoft, Xilinx, Barefoot, and Google. P4 is open source and owned by everyone. The language is carefully designed to be target independent and can be used to program any programmable forwarding device. So far, it has been used to program a variety of software and hardware switches and NICs from different sources. See P4.org for more details.
P4 is more general than OpenFlow, allowing users to define exactly how the forwarding plane processes packets. OpenFlow can be expressed in the P4 language; openflow.p4 provides a helpful way to get started.
This is a very valid question for a switch that is based on a fixed-function ASIC. Intel® Tofino™ is highly programmable, consisting of multiple pipelines and Match Action Units (MAU) inside each pipeline. An MAU contains a flexible parsing logic and multiple SRAM and TCAM table blocks that can be carved to accommodate a specific deployment. Intel can provide sample verified scalability numbers based on a reference P4 program and under NDA. However, they should never be interpreted as maximum theoretical scalability values of the chip.
Programmability enables limitless flexibility and multiple use cases, ranging from the customization of the switch table sizes for efficient scale to the enhancement of the existing networking functions and the addition of new capabilities such as telemetry, security, and load balancing.
Absolutely! You should ask your vendor about their support for Intel® Tofino™ in their switching platform. Once the Intel® Tofino™-based platform is offered, you should be in full power to make data-plane feature requests and expect a feature delivery road map on the existing ASIC.
P4 is an Apache-licensed open source language owned by P4.org, an independent nonprofit. Any company, university, or individual can join P4.org free and contribute to the language, compiler, and tools. Intel is one of over 100 members of P4.org, including companies from all across our industry, from AT&T to ZTE, and some of the world’s top universities. The P4.org Advisory Board consists of Amin Vahdat (Google), Jennifer Rexford (Princeton), Nate Foster (Cornell), Guru Parulkar (ONF), and Nick McKeown (Stanford/Intel). The language was designed by world experts in programming language design from Princeton, Cornell, Stanford, VMware, Intel, Microsoft, Xilinx, Barefoot, and Google. P4 is open source and owned by everyone. The language is carefully designed to be target independent and can be used to program any programmable forwarding device. So far, it has been used to program a variety of software and hardware switches and NICs from different sources. See P4.org for more details.
P4 is more general than OpenFlow, allowing users to define exactly how the forwarding plane processes packets. OpenFlow can be expressed in the P4 language; openflow.p4 provides a helpful way to get started.
This is a very valid question for a switch that is based on a fixed-function ASIC. Intel® Tofino™ is highly programmable, consisting of multiple pipelines and Match Action Units (MAU) inside each pipeline. An MAU contains a flexible parsing logic and multiple SRAM and TCAM table blocks that can be carved to accommodate a specific deployment. Intel can provide sample verified scalability numbers based on a reference P4 program and under NDA. However, they should never be interpreted as maximum theoretical scalability values of the chip.
Programmability enables limitless flexibility and multiple use cases, ranging from the customization of the switch table sizes for efficient scale to the enhancement of the existing networking functions and the addition of new capabilities such as telemetry, security, and load balancing.
Absolutely! You should ask your vendor about their support for Intel® Tofino™ in their switching platform. Once the Intel® Tofino™-based platform is offered, you should be in full power to make data-plane feature requests and expect a feature delivery road map on the existing ASIC.