Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 MX FPGA is the essential multi-function accelerator for high performance computing (HPC), data center, virtual networking functions (NFV), and broadcast applications. These devices combine the programmability and flexibility of Intel® Stratix® 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The Intel® Hyperflex™ FPGA Architecture enables high-performance core fabric that can efficiently utilize the bandwidth from the in-package memory tile. The DRAM memory tile is physically connected to the FPGA using Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology.
Intel® Stratix® 10 MX FPGA
Features & Benefits
Higher Memory Bandwidth
Intel® Stratix® 10 MX devices offer 10X more bandwidth versus current discrete memory solutions such as DDR4 SDRAM. Traditional DDR4 DIMMs provide ~21 GBps bandwidth while 1 HBM2 tile provides up to 256 GBps. Intel® Stratix® 10 MX devices integrate up to two HBM2 devices in a single package, enabling a maximum memory bandwidth of up to 512 GBps.
Lower Power and Optimum Performance/Watt
Intel® Stratix® 10 MX devices integrate HBM2 memory next to the core fabric. The interconnect between the core fabric and memory is significantly shorter, which reduces the amount of power traditionally spent driving long PCB traces. The traces are unterminated and there is reduced capacitive loading, which results in lower I/O current consumption. The net result is lower system power and optimum performance per watt.
Factor and Ease of Use
The Intel® Stratix® 10 MX package integrates memory components, reducing the complexity of the PCB design. This implementation enables a smaller form factor and a simple usage model, resulting in a highly flexible, easy to use, scalable solution. One example of this feature is with the embedded SRAM (eSRAM), which supplements already existing block RAM with higher bandwidth 11.25X more aggregate (read and write) bandwidth and 2.6X total lower power relative to discrete QDR IV-10661.The enhanced embedded SRAM is ideal for applications requiring highest levels of random transaction rates (RTR), helping replace or minimize the need for discrete QDR, and zero EMIF I/O consumption.
SiP integration using EMIB, enables the highest interconnect density between FPGA and the companion die. This arrangement results in high bandwidth connectivity between the SiP components.
Companion die (such as memory) are placed as close as possible to the FPGA. The interconnect traces between the FPGA and the companion die are thus very short and do not need as much power to drive them, resulting in lower overall power and optimum performance/watt.
The ability to heterogeneously integrate components in a single package results in smaller form factors. Customers save valuable board space, reduce board layers, and overall bill of material (BOM) cost.
SiP helps reduce routing complexity at the PCB level because the components are already integrated within the package.
Mixed Process Nodes
SiP enhances the ability to incorporate different die geometries and silicon technologies. The net result is a highly flexible, scalable solution that is easy to use.
Faster Time to Market
SiP enables faster time to market by integrating already proven technology and reusing common devices or tiles across product variants. This implementation saves valuable time and resources, thereby accelerating time to market.
Chip-Level Integration Using EMIB
An innovative Embedded Multi-Die Interconnect Bridge (EMIB) packaging technology, developed by Intel, enables effective in-package integration of system-critical components such as analog, memory, ASICs, CPU, etc. EMIB offers a simpler manufacturing flow compared to other in-package integration technologies. EMIB eliminates the use of through silicon vias (TSV) and specialized interposer silicon. The result is highly integrated, system-in-package products that offer higher performance, less complexity, and superior signal and power integrity. Additional information about Intel’s EMIB technology can be found on the Intel Custom Foundry website located at http://www.intel.com/content/www/us/en/foundry/emib.html
- Chip-to-chip bandwidth is limited.
- System power is too high.
- Form factor is too big.
Heterogeneous SiP Approach
- Higher bandwidth.
- Lower power.
- Smaller form factor.
- Increased functionality.
- Ability to mix process nodes.
FPGAs with Near Memory in Package
Intel's near memory solutions integrate high-density DRAM close to the FPGA, within the same package. In this configuration, the in-package memory is accessible significantly faster, up to 10X higher bandwidth when compared to traditional main memory. A near-memory configuration also reduces system power by reducing traces between the FPGA and memory, while also reducing board area.
DRAM system-in-package (SiP) solutions leverage high-bandwidth memory 2 (HBM2) to eliminate memory bandwidth bottlenecks in high-performance systems that are processing an ever-increasing amount of data; including data center, broadcast, wireline networking, and high-performance computing systems.
HBM2 DRAM is a 3D memory that vertically stacks multiple DRAM die using through silicon via (TSV) technology. Compared to discrete DDR-based solutions, HBM2 DRAM provides higher memory bandwidth, lower system power, and smaller form factor, thereby providing the best bandwidth/watt.
Intel® Stratix® 10 MX devices integrate HBM2 tiles alongside a high-performance monolithic 14 nm FPGA die to offer over 10X higher memory bandwidth relative to discrete DRAM solutions.
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