ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartus-11.1-1.dp11-readme.txt Readme file for Quartus II 11.1 SP1 Patch 1.dp11 Copyright (C) Altera Corporation 2012 All right reserved. Patch created on January 24 2012 Patch SPR#: 393115 //**************************************************************** Please note, this patch is meant to address known software issues for Stratix V and Arria V devices in the Quartus II software version 11.1 SP1. The device patches are cumulative. For example, you can install 1.dp11 over 1.dp5 or 1.dp3 or 1.dp2 patch or directly on top of 11.1 SP1. ---------------- Issue 1 (393196) ---------------- Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_io.cpp, Line: 5702 ---------------- Issue 2 (393150) ---------------- This patch provides device support for ArriaV 5AGXMB3E6F29C6ES under dev password control. ---------------- Issue 3 (393065) ---------------- In some case, the fractional PLL would fail to provide clock when sourcing from certain HSSI refclk pin. ---------------- Issue 4 (392937) ---------------- TX_forceelecidle is always asserted on Stratix V 5SGXB6 ES devices. TX buffers won't output unless this pin is deasserted. ---------------- Issue 5 (392782) ---------------- Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/place_congestion.c, Line: 2194 ---------------- Issue 6 (393305) ---------------- TimeQuest runtime is 3 times longer in v11.1 compared to v10.1 SP1 An optimization bug in handling clock tree nodes that drive feedback registers was fixed. The bug resulted in more than requried timing analysis units to analyze and hence the bump in run time. The effect of the fix can be seen in faster runtime of TimeQuest. ---------------- Issue 7 (393304) ---------------- Certain power supply relationship would cause the transceiver TX buffer to power down on 5SGXA7 ES and 5SGXB6 ES devices. This patch prevents the buffer from powering down. ---------------- Issue 8 (393301) ---------------- This patch updates timing models and fitter timing optimization of the Stratix V 5SGXA7 ES device. Timing delays on routing wires from core to IO and IO to core, particularly for corner I/Os have been updated and made more accurate through silicon correlation. It is recommended that designs should be re-run through fitter and timing analysis for timing closure. ---------------- Issue 9 (393297) ---------------- If an atom parameter had a data rate more than 2 Gbps, the value taken into account by Quartus was significantly smaller and could result in incorrect settings for the following parameters: common_mode_driver_sel eq_bw_sel ----------------- Issue 10 (393187) ----------------- Altera PLL Reconfig MegaWizard is not able to load. ----------------- Issue 11 (393224) ----------------- This patch provides a more stable PLL configuration when using the ATX PLL in higher frequency applications for Stratix V ES devices. ----------------- Issue 12 (393398) ----------------- This patch updates the delays between the bottom-left corner IOs and the core based on more accurate models for Stratix V ES devices. ----------------- Issue 13 (393386) ----------------- When design is targeting Arria V Hard IP for PCI Express with bar1 - 32-bit non-prefetchable in the Megawizard, compilation runs into Analysis and Synthesis error as below: Error: Hard IP parameter 'hd_altpe2_hip_top_bar1_prefetchable_0' is set to an illegal value of 'false' on node . ----------------- Issue 14 (393556) ----------------- Stratix V M20K read data corruption - output MUX seems to wrongly select data at ram block switching. This is due to the CBX_ALTSYNCRAM missing a register before the output select mux. Without the register, the output mux which is controlled by the MSB of the address bits will get the address updated one clock cycle earlier and select the output from the next RAM block. The issue will only occur when M20K hard ECC feature is turned ON and with ECC pipeline register used on a large logical RAM that requires multiple M20K usage. ----------------- Issue 15 (391270) ----------------- Quartus II Fitter gives the following error when a clock feeds FPLL and then feeds 10Gbase reference clock: Error (175001): Could not place global or regional clock driver fpll:U_fpll|fpll_0002:fpll_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 Error (177012): Route from PLL output counter output fpll:U_fpll|fpll_0002:fpll_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER to global or regional clock driver fpll:U_fpll|fpll_0002:fpll_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 is over congested Error (184040): fractional PLL fpll:U_fpll|fpll_0002:fpll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL was placed into device location "PLLOUTPUTCOUNTER_X210_Y43_N1" Error (184041): global or regional clock driver fpll:U_fpll|fpll_0002:fpll_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 could not be placed into any device location to satisfy its connectivity requirements ----------------- Issue 16 (393488) ----------------- Quartus II triggers the following error in the Stratix V DDR legality checks: Fatal Error: Access Violation at 0X000000000725E2DC This can happen to Stratix V design with a constant input going into a delay chain. ----------------- Issue 17 (31470) ----------------- Quartus II Analysis and Elaboration takes an unexpectedly long time to complete when a design has a large number of hierarchies, or uses relative include paths in source code, or has source codes in a directory outside of the project directory. ----------------- Issue 18 (31645) ----------------- Quartus II triggers the following error when openning Chip Planner for Stratix V designs with DQS FF: Fatal Error: Access Violation at 0X000000001CED28C5 ----------------- Issue 19 (31896) ----------------- This patch allows 3.3lvttl and 2.5v inputs to be placed in the same IO bank. This feature is supported under INI control. ----------------- Issue 20 (32085) ----------------- Stratix V PLL phase_done is stuck at low. ----------------- Issue 21 (32089) ----------------- This patch updates the following timing models for Stratix V F5ES devices: Several C4 wires near the M20K and DSP blocks PCLK models that affect all PCLKs ----------------- Issue 22 (32258) ----------------- This patch updates M counter PLL delay chain settings for LVDS clock compensation. ----------------- Issue 23 (32785) ----------------- Alt_syncram is missing some timing paths for Stratix V M20K ECC modes. ----------------- Issue 24 (33242) ----------------- This patch sets correct single-ended I/O standard for 1.25V and 1.35V for Stratix V devices. ----------------- Issue 25 (33492) ----------------- This patch adds location dependent PLL delay chain settings for LVDS mode for Stratix V devices. ----------------- Issue 26 (33894) ----------------- Internal Error: Sub-system: ASMCC, File: /quartus/comp/asmcc/asmcc_bitfield.cpp, Line: 882 Assembler bitfield error: Found conflicting assignments for CRAM address; address = 4935431 ----------------- Issue 27 (34197) ----------------- Internal Error: Sub-system: ASMIO, File: /quartus/comp/asmio/asmio_oct.cpp, Line: 714 !is_differential ----------------- Issue 28 (34212) ----------------- Address decoder in Stratix V soft XAUI had incorrect connection, making registers in address range 0x40 -0x7F inaccessible. Caution - You must either have previously installed the Quartus II 11.1 SP1 software or must install the Quartus II 11.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.