xcvr_test_system

2015.03.25.15:32:34 Datasheet
Overview
  clk_50  xcvr_test_system

All Components
   data_pattern_checker_x32_g0 altera_avalon_data_pattern_checker 15.0
   data_pattern_checker_x32_g1 altera_avalon_data_pattern_checker 15.0
   data_pattern_checker_x32_g2 altera_avalon_data_pattern_checker 15.0
   data_pattern_checker_x40_g3 altera_avalon_data_pattern_checker 15.0
   data_pattern_generator_x32_g0 altera_avalon_data_pattern_generator 15.0
   data_pattern_generator_x32_g1 altera_avalon_data_pattern_generator 15.0
   data_pattern_generator_x32_g2 altera_avalon_data_pattern_generator 15.0
   data_pattern_generator_x40_g3 altera_avalon_data_pattern_generator 15.0
   pio_0 altera_avalon_pio 15.0
   pio_1 altera_avalon_pio 15.0
   pio_2 altera_avalon_pio 15.0
Memory Map
master_0
 master
  data_pattern_checker_x32_g0
csr_slave  0x00000000
  data_pattern_checker_x32_g1
csr_slave  0x00000020
  data_pattern_checker_x32_g2
csr_slave  0x00000040
  data_pattern_checker_x40_g3
csr_slave  0x00000060
  data_pattern_generator_x32_g0
csr_slave  0x00000080
  data_pattern_generator_x32_g1
csr_slave  0x000000a0
  data_pattern_generator_x32_g2
csr_slave  0x000000c0
  data_pattern_generator_x40_g3
csr_slave  0x000000e0
  pio_0
s1  0x00000100
  pio_1
s1  0x00000110
  pio_2
s1  0x00000120

clk_50

clock_source v15.0


Parameters

clockFrequency 500000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_x32_g0

altera_avalon_data_pattern_checker v15.0
master_0 master   data_pattern_checker_x32_g0
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset


Parameters

ST_DATA_W 32
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 4
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CSR_CLK_CLOCK_RATE 500000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_x32_g1

altera_avalon_data_pattern_checker v15.0
master_0 master   data_pattern_checker_x32_g1
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset


Parameters

ST_DATA_W 32
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 4
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CSR_CLK_CLOCK_RATE 500000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_x32_g2

altera_avalon_data_pattern_checker v15.0
master_0 master   data_pattern_checker_x32_g2
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset


Parameters

ST_DATA_W 32
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 4
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CSR_CLK_CLOCK_RATE 500000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

data_pattern_checker_x40_g3

altera_avalon_data_pattern_checker v15.0
master_0 master   data_pattern_checker_x40_g3
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 4
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CSR_CLK_CLOCK_RATE 500000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_x32_g0

altera_avalon_data_pattern_generator v15.0
master_0 master   data_pattern_generator_x32_g0
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset


Parameters

ST_DATA_W 32
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 4
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CSR_CLK_CLOCK_RATE 500000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_x32_g1

altera_avalon_data_pattern_generator v15.0
master_0 master   data_pattern_generator_x32_g1
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset


Parameters

ST_DATA_W 32
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 4
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CSR_CLK_CLOCK_RATE 500000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_x32_g2

altera_avalon_data_pattern_generator v15.0
master_0 master   data_pattern_generator_x32_g2
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset


Parameters

ST_DATA_W 32
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 4
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CSR_CLK_CLOCK_RATE 500000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

data_pattern_generator_x40_g3

altera_avalon_data_pattern_generator v15.0
master_0 master   data_pattern_generator_x40_g3
  csr_slave
clk_50 clk  
  csr_clk
clk_reset  
  reset


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 4
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CSR_CLK_CLOCK_RATE 500000000
AUTO_CSR_CLK_CLOCK_DOMAIN 1
AUTO_CSR_CLK_RESET_DOMAIN 1
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

master_0

altera_jtag_avalon_master v15.0
clk_50 clk   master_0
  clk
clk_reset  
  clk_reset
master   data_pattern_generator_x40_g3
  csr_slave
master   data_pattern_generator_x32_g2
  csr_slave
master   data_pattern_generator_x32_g1
  csr_slave
master   data_pattern_generator_x32_g0
  csr_slave
master   data_pattern_checker_x40_g3
  csr_slave
master   data_pattern_checker_x32_g2
  csr_slave
master   data_pattern_checker_x32_g1
  csr_slave
master   data_pattern_checker_x32_g0
  csr_slave
master   pio_0
  s1
master   pio_1
  s1
master   pio_2
  s1


Parameters

USE_PLI 0
PLI_PORT 50000
COMPONENT_CLOCK 0
FAST_VER 0
FIFO_DEPTHS 2
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

pio_0

altera_avalon_pio v15.0
master_0 master   pio_0
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 17
clockRate 500000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 17
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 500000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_1

altera_avalon_pio v15.0
master_0 master   pio_1
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 17
clockRate 500000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 17
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 500000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_2

altera_avalon_pio v15.0
master_0 master   pio_2
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
clockRate 500000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 500000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0
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