adc_qsys

2015.03.25.13:46:05 Datasheet
Overview
  clk_50m  adc_qsys
  clk_adc_ref 

All Components
   dac_ctrl altera_avalon_pio 15.0
   modular_adc_0 altera_modular_adc 15.0
   modular_adc_1 altera_modular_adc 15.0
   product_info_0 product_info 1.0
Memory Map
master_0
 master
  dac_ctrl
s1  0x00000010
  modular_adc_0
sequencer_csr  0x00001000
sample_store_csr  0x00001200
  modular_adc_1
sequencer_csr  0x00002000
sample_store_csr  0x00002200
  product_info_0
avalon_slave_0  0x00000000

clk_50m

clock_source v15.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

clk_adc_ref

clock_source v15.0


Parameters

clockFrequency 10000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

dac_ctrl

altera_avalon_pio v15.0
master_0 master   dac_ctrl
  s1
clk_50m clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 18
clockRate 50000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 18
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

master_0

altera_jtag_avalon_master v15.0
clk_50m clk   master_0
  clk
clk_reset  
  clk_reset
master   product_info_0
  avalon_slave_0
master   dac_ctrl
  s1
master   modular_adc_0
  sample_store_csr
master  
  sequencer_csr
master   modular_adc_1
  sample_store_csr
master  
  sequencer_csr


Parameters

USE_PLI 0
PLI_PORT 50000
COMPONENT_CLOCK 0
FAST_VER 0
FIFO_DEPTHS 2
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

modular_adc_0

altera_modular_adc v15.0
master_0 master   modular_adc_0
  sample_store_csr
master  
  sequencer_csr
clk_adc_ref clk  
  adc_pll_clock
clk_reset  
  reset_sink
clk_50m clk  
  clock
clk_reset  
  reset_sink


Parameters

CORE_VAR 0
ENABLE_DEBUG 0
MONITOR_COUNT_WIDTH 12
CLOCK_FREQ 50000000
FAMILY MAX10FPGA
DEVICE_PART 10M50DAF484C6GES
device_partname_fivechar_prefix 10M50
device_adc_type 33
max_adc_count_on_die 2
adc_count_on_device 2
device_power_supply_type 2
ip_is_for_which_adc 1
is_this_first_or_second_adc 1
analog_input_pin_mask 0
hard_pwd 0
clkdiv 2
tsclkdiv 1
tsclksel 1
refsel 0
external_vref 2.5
int_vref_vr 3.0
int_vref_nonvr 2.5
reference_voltage 2.5
prescalar 0
use_tsd true
en_tsd_max false
tsd_max 125
en_tsd_min false
tsd_min 0
use_ch0 true
en_thmax_ch0 false
thmax_ch0 0.0
en_thmin_ch0 false
thmin_ch0 0.0
use_ch1 true
en_thmax_ch1 false
thmax_ch1 0.0
en_thmin_ch1 false
thmin_ch1 0.0
use_ch2 true
en_thmax_ch2 false
thmax_ch2 0.0
en_thmin_ch2 false
thmin_ch2 0.0
use_ch3 true
en_thmax_ch3 false
thmax_ch3 0.0
en_thmin_ch3 false
thmin_ch3 0.0
use_ch4 true
en_thmax_ch4 false
thmax_ch4 0.0
en_thmin_ch4 false
thmin_ch4 0.0
use_ch5 true
en_thmax_ch5 false
thmax_ch5 0.0
en_thmin_ch5 false
thmin_ch5 0.0
use_ch6 true
en_thmax_ch6 false
thmax_ch6 0.0
en_thmin_ch6 false
thmin_ch6 0.0
use_ch7 true
en_thmax_ch7 false
thmax_ch7 0.0
en_thmin_ch7 false
thmin_ch7 0.0
use_ch8 true
prescaler_ch8 false
en_thmax_ch8 false
thmax_ch8 0.0
en_thmin_ch8 false
thmin_ch8 0.0
use_ch9 false
en_thmax_ch9 false
thmax_ch9 0.0
en_thmin_ch9 false
thmin_ch9 0.0
use_ch10 false
en_thmax_ch10 false
thmax_ch10 0.0
en_thmin_ch10 false
thmin_ch10 0.0
use_ch11 false
en_thmax_ch11 false
thmax_ch11 0.0
en_thmin_ch11 false
thmin_ch11 0.0
use_ch12 false
en_thmax_ch12 false
thmax_ch12 0.0
en_thmin_ch12 false
thmin_ch12 0.0
use_ch13 false
en_thmax_ch13 false
thmax_ch13 0.0
en_thmin_ch13 false
thmin_ch13 0.0
use_ch14 false
en_thmax_ch14 false
thmax_ch14 0.0
en_thmin_ch14 false
thmin_ch14 0.0
use_ch15 false
en_thmax_ch15 false
thmax_ch15 0.0
en_thmin_ch15 false
thmin_ch15 0.0
use_ch16 false
prescaler_ch16 false
en_thmax_ch16 false
thmax_ch16 0.0
en_thmin_ch16 false
thmin_ch16 0.0
seq_order_length 10
seq_order_slot_1 0
seq_order_slot_2 1
seq_order_slot_3 2
seq_order_slot_4 3
seq_order_slot_5 4
seq_order_slot_6 5
seq_order_slot_7 6
seq_order_slot_8 7
seq_order_slot_9 8
seq_order_slot_10 17
seq_order_slot_11 30
seq_order_slot_12 30
seq_order_slot_13 30
seq_order_slot_14 30
seq_order_slot_15 30
seq_order_slot_16 30
seq_order_slot_17 30
seq_order_slot_18 30
seq_order_slot_19 30
seq_order_slot_20 30
seq_order_slot_21 30
seq_order_slot_22 30
seq_order_slot_23 30
seq_order_slot_24 30
seq_order_slot_25 30
seq_order_slot_26 30
seq_order_slot_27 30
seq_order_slot_28 30
seq_order_slot_29 30
seq_order_slot_30 30
seq_order_slot_31 30
seq_order_slot_32 30
seq_order_slot_33 30
seq_order_slot_34 30
seq_order_slot_35 30
seq_order_slot_36 30
seq_order_slot_37 30
seq_order_slot_38 30
seq_order_slot_39 30
seq_order_slot_40 30
seq_order_slot_41 30
seq_order_slot_42 30
seq_order_slot_43 30
seq_order_slot_44 30
seq_order_slot_45 30
seq_order_slot_46 30
seq_order_slot_47 30
seq_order_slot_48 30
seq_order_slot_49 30
seq_order_slot_50 30
seq_order_slot_51 30
seq_order_slot_52 30
seq_order_slot_53 30
seq_order_slot_54 30
seq_order_slot_55 30
seq_order_slot_56 30
seq_order_slot_57 30
seq_order_slot_58 30
seq_order_slot_59 30
seq_order_slot_60 30
seq_order_slot_61 30
seq_order_slot_62 30
seq_order_slot_63 30
seq_order_slot_64 30
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CORE_VARIANT 0
CSD_LENGTH 10
CSD_SLOT_0 CH0
CSD_SLOT_1 CH1
CSD_SLOT_10 CH0
CSD_SLOT_11 CH0
CSD_SLOT_12 CH0
CSD_SLOT_13 CH0
CSD_SLOT_14 CH0
CSD_SLOT_15 CH0
CSD_SLOT_16 CH0
CSD_SLOT_17 CH0
CSD_SLOT_18 CH0
CSD_SLOT_19 CH0
CSD_SLOT_2 CH2
CSD_SLOT_20 CH0
CSD_SLOT_21 CH0
CSD_SLOT_22 CH0
CSD_SLOT_23 CH0
CSD_SLOT_24 CH0
CSD_SLOT_25 CH0
CSD_SLOT_26 CH0
CSD_SLOT_27 CH0
CSD_SLOT_28 CH0
CSD_SLOT_29 CH0
CSD_SLOT_3 CH3
CSD_SLOT_30 CH0
CSD_SLOT_31 CH0
CSD_SLOT_32 CH0
CSD_SLOT_33 CH0
CSD_SLOT_34 CH0
CSD_SLOT_35 CH0
CSD_SLOT_36 CH0
CSD_SLOT_37 CH0
CSD_SLOT_38 CH0
CSD_SLOT_39 CH0
CSD_SLOT_4 CH4
CSD_SLOT_40 CH0
CSD_SLOT_41 CH0
CSD_SLOT_42 CH0
CSD_SLOT_43 CH0
CSD_SLOT_44 CH0
CSD_SLOT_45 CH0
CSD_SLOT_46 CH0
CSD_SLOT_47 CH0
CSD_SLOT_48 CH0
CSD_SLOT_49 CH0
CSD_SLOT_5 CH5
CSD_SLOT_50 CH0
CSD_SLOT_51 CH0
CSD_SLOT_52 CH0
CSD_SLOT_53 CH0
CSD_SLOT_54 CH0
CSD_SLOT_55 CH0
CSD_SLOT_56 CH0
CSD_SLOT_57 CH0
CSD_SLOT_58 CH0
CSD_SLOT_59 CH0
CSD_SLOT_6 CH6
CSD_SLOT_60 CH0
CSD_SLOT_61 CH0
CSD_SLOT_62 CH0
CSD_SLOT_63 CH0
CSD_SLOT_7 CH7
CSD_SLOT_8 CH8
CSD_SLOT_9 TSD
DUAL_ADC_MODE false
IS_THIS_FIRST_OR_SECOND_ADC 1
PRESCALER_CH16 0
PRESCALER_CH8 0
REFSEL External VREF
USE_CH0 1
USE_CH1 1
USE_CH10 0
USE_CH11 0
USE_CH12 0
USE_CH13 0
USE_CH14 0
USE_CH15 0
USE_CH16 0
USE_CH2 1
USE_CH3 1
USE_CH4 1
USE_CH5 1
USE_CH6 1
USE_CH7 1
USE_CH8 1
USE_CH9 0
USE_TSD 1
VREF 2.5

modular_adc_1

altera_modular_adc v15.0
master_0 master   modular_adc_1
  sample_store_csr
master  
  sequencer_csr
clk_adc_ref clk  
  adc_pll_clock
clk_reset  
  reset_sink
clk_50m clk  
  clock
clk_reset  
  reset_sink


Parameters

CORE_VAR 0
ENABLE_DEBUG 0
MONITOR_COUNT_WIDTH 12
CLOCK_FREQ 50000000
FAMILY MAX10FPGA
DEVICE_PART 10M50DAF484C6GES
device_partname_fivechar_prefix 10M50
device_adc_type 33
max_adc_count_on_die 2
adc_count_on_device 2
device_power_supply_type 2
ip_is_for_which_adc 2
is_this_first_or_second_adc 2
analog_input_pin_mask 0
hard_pwd 0
clkdiv 2
tsclkdiv 1
tsclksel 1
refsel 0
external_vref 2.5
int_vref_vr 3.0
int_vref_nonvr 2.5
reference_voltage 2.5
prescalar 0
use_tsd true
en_tsd_max false
tsd_max 125
en_tsd_min false
tsd_min 0
use_ch0 true
en_thmax_ch0 false
thmax_ch0 0.0
en_thmin_ch0 false
thmin_ch0 0.0
use_ch1 true
en_thmax_ch1 false
thmax_ch1 0.0
en_thmin_ch1 false
thmin_ch1 0.0
use_ch2 true
en_thmax_ch2 false
thmax_ch2 0.0
en_thmin_ch2 false
thmin_ch2 0.0
use_ch3 true
en_thmax_ch3 false
thmax_ch3 0.0
en_thmin_ch3 false
thmin_ch3 0.0
use_ch4 true
en_thmax_ch4 false
thmax_ch4 0.0
en_thmin_ch4 false
thmin_ch4 0.0
use_ch5 true
en_thmax_ch5 false
thmax_ch5 0.0
en_thmin_ch5 false
thmin_ch5 0.0
use_ch6 true
en_thmax_ch6 false
thmax_ch6 0.0
en_thmin_ch6 false
thmin_ch6 0.0
use_ch7 true
en_thmax_ch7 false
thmax_ch7 0.0
en_thmin_ch7 false
thmin_ch7 0.0
use_ch8 true
prescaler_ch8 false
en_thmax_ch8 false
thmax_ch8 0.0
en_thmin_ch8 false
thmin_ch8 0.0
use_ch9 false
en_thmax_ch9 false
thmax_ch9 0.0
en_thmin_ch9 false
thmin_ch9 0.0
use_ch10 false
en_thmax_ch10 false
thmax_ch10 0.0
en_thmin_ch10 false
thmin_ch10 0.0
use_ch11 false
en_thmax_ch11 false
thmax_ch11 0.0
en_thmin_ch11 false
thmin_ch11 0.0
use_ch12 false
en_thmax_ch12 false
thmax_ch12 0.0
en_thmin_ch12 false
thmin_ch12 0.0
use_ch13 false
en_thmax_ch13 false
thmax_ch13 0.0
en_thmin_ch13 false
thmin_ch13 0.0
use_ch14 false
en_thmax_ch14 false
thmax_ch14 0.0
en_thmin_ch14 false
thmin_ch14 0.0
use_ch15 false
en_thmax_ch15 false
thmax_ch15 0.0
en_thmin_ch15 false
thmin_ch15 0.0
use_ch16 false
prescaler_ch16 false
en_thmax_ch16 false
thmax_ch16 0.0
en_thmin_ch16 false
thmin_ch16 0.0
seq_order_length 9
seq_order_slot_1 0
seq_order_slot_2 1
seq_order_slot_3 2
seq_order_slot_4 3
seq_order_slot_5 4
seq_order_slot_6 5
seq_order_slot_7 6
seq_order_slot_8 7
seq_order_slot_9 8
seq_order_slot_10 17
seq_order_slot_11 30
seq_order_slot_12 30
seq_order_slot_13 30
seq_order_slot_14 30
seq_order_slot_15 30
seq_order_slot_16 30
seq_order_slot_17 30
seq_order_slot_18 30
seq_order_slot_19 30
seq_order_slot_20 30
seq_order_slot_21 30
seq_order_slot_22 30
seq_order_slot_23 30
seq_order_slot_24 30
seq_order_slot_25 30
seq_order_slot_26 30
seq_order_slot_27 30
seq_order_slot_28 30
seq_order_slot_29 30
seq_order_slot_30 30
seq_order_slot_31 30
seq_order_slot_32 30
seq_order_slot_33 30
seq_order_slot_34 30
seq_order_slot_35 30
seq_order_slot_36 30
seq_order_slot_37 30
seq_order_slot_38 30
seq_order_slot_39 30
seq_order_slot_40 30
seq_order_slot_41 30
seq_order_slot_42 30
seq_order_slot_43 30
seq_order_slot_44 30
seq_order_slot_45 30
seq_order_slot_46 30
seq_order_slot_47 30
seq_order_slot_48 30
seq_order_slot_49 30
seq_order_slot_50 30
seq_order_slot_51 30
seq_order_slot_52 30
seq_order_slot_53 30
seq_order_slot_54 30
seq_order_slot_55 30
seq_order_slot_56 30
seq_order_slot_57 30
seq_order_slot_58 30
seq_order_slot_59 30
seq_order_slot_60 30
seq_order_slot_61 30
seq_order_slot_62 30
seq_order_slot_63 30
seq_order_slot_64 30
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CORE_VARIANT 0
CSD_LENGTH 9
CSD_SLOT_0 CH0
CSD_SLOT_1 CH1
CSD_SLOT_10 CH0
CSD_SLOT_11 CH0
CSD_SLOT_12 CH0
CSD_SLOT_13 CH0
CSD_SLOT_14 CH0
CSD_SLOT_15 CH0
CSD_SLOT_16 CH0
CSD_SLOT_17 CH0
CSD_SLOT_18 CH0
CSD_SLOT_19 CH0
CSD_SLOT_2 CH2
CSD_SLOT_20 CH0
CSD_SLOT_21 CH0
CSD_SLOT_22 CH0
CSD_SLOT_23 CH0
CSD_SLOT_24 CH0
CSD_SLOT_25 CH0
CSD_SLOT_26 CH0
CSD_SLOT_27 CH0
CSD_SLOT_28 CH0
CSD_SLOT_29 CH0
CSD_SLOT_3 CH3
CSD_SLOT_30 CH0
CSD_SLOT_31 CH0
CSD_SLOT_32 CH0
CSD_SLOT_33 CH0
CSD_SLOT_34 CH0
CSD_SLOT_35 CH0
CSD_SLOT_36 CH0
CSD_SLOT_37 CH0
CSD_SLOT_38 CH0
CSD_SLOT_39 CH0
CSD_SLOT_4 CH4
CSD_SLOT_40 CH0
CSD_SLOT_41 CH0
CSD_SLOT_42 CH0
CSD_SLOT_43 CH0
CSD_SLOT_44 CH0
CSD_SLOT_45 CH0
CSD_SLOT_46 CH0
CSD_SLOT_47 CH0
CSD_SLOT_48 CH0
CSD_SLOT_49 CH0
CSD_SLOT_5 CH5
CSD_SLOT_50 CH0
CSD_SLOT_51 CH0
CSD_SLOT_52 CH0
CSD_SLOT_53 CH0
CSD_SLOT_54 CH0
CSD_SLOT_55 CH0
CSD_SLOT_56 CH0
CSD_SLOT_57 CH0
CSD_SLOT_58 CH0
CSD_SLOT_59 CH0
CSD_SLOT_6 CH6
CSD_SLOT_60 CH0
CSD_SLOT_61 CH0
CSD_SLOT_62 CH0
CSD_SLOT_63 CH0
CSD_SLOT_7 CH7
CSD_SLOT_8 CH8
CSD_SLOT_9 CH0
DUAL_ADC_MODE false
IS_THIS_FIRST_OR_SECOND_ADC 2
PRESCALER_CH16 0
PRESCALER_CH8 0
REFSEL External VREF
USE_CH0 1
USE_CH1 1
USE_CH10 0
USE_CH11 0
USE_CH12 0
USE_CH13 0
USE_CH14 0
USE_CH15 0
USE_CH16 0
USE_CH2 1
USE_CH3 1
USE_CH4 1
USE_CH5 1
USE_CH6 1
USE_CH7 1
USE_CH8 1
USE_CH9 0
USE_TSD 1
VREF 2.5

product_info_0

product_info v1.0
master_0 master   product_info_0
  avalon_slave_0
clk_50m clk  
  clock_reset
clk_reset  
  clock_reset_reset


Parameters

AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_CLOCK_RESET_CLOCK_RATE 50000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)
generation took 0.01 seconds rendering took 0.05 seconds