q_sys

2015.03.25.20:35:53 Datasheet
Overview
  sys_clk  q_sys
Processor
   cpu Nios II 15.0
All Components
   altpll_shift altpll 15.0
   cpu altera_nios2_gen2 15.0
   descriptor_memory altera_avalon_onchip_memory2 15.0
   enet_pll altpll 15.0
   eth_tse altera_eth_tse 15.0
   ext_flash altera_generic_quad_spi_controller 15.0
   jtag_uart altera_avalon_jtag_uart 15.0
   led_pio altera_avalon_pio 15.0
   mem_if_ddr3_emif_0 altera_mem_if_ddr3_emif 15.0
   onchip_ram altera_avalon_onchip_memory2 15.0
   sgdma_rx altera_avalon_sgdma 15.0
   sgdma_tx altera_avalon_sgdma 15.0
   sys_clk_timer altera_avalon_timer 15.0
   sysid altera_avalon_sysid_qsys 15.0
Memory Map
cpu sgdma_rx sgdma_tx
 data_master  instruction_master  descriptor_read  descriptor_write  m_write  descriptor_read  descriptor_write  m_read
  altpll_shift
pll_slave 
  cpu
debug_mem_slave  0x00200800 0x00200800
  descriptor_memory
s1  0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  enet_pll
pll_slave 
  eth_tse
control_port  0x00201000
  ext_flash
avl_csr  0x20000000 0x20000000
avl_mem  0x24000000 0x24000000
  jtag_uart
avalon_jtag_slave  0x002016b0
  led_pio
s1  0x002016c0
  mem_if_ddr3_emif_0
avl  0x10000000 0x10000000 0x10000000 0x10000000
  onchip_ram
s1  0x00201800
  sgdma_rx
csr  0x00201600
  sgdma_tx
csr  0x00201640
  sys_clk_timer
s1  0x00201680
  sysid
control_slave  0x002016b8

altpll_shift

altpll v15.0
sys_clk clk   altpll_shift
  inclk_interface
mem_resetn out_reset  
  inclk_interface_reset


Parameters

HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY MAX 10
WIDTH_CLOCK 5
WIDTH_PHASECOUNTERSELECT
PRIMARY_CLOCK
INCLK0_INPUT_FREQUENCY 20000
INCLK1_INPUT_FREQUENCY
OPERATION_MODE NORMAL
PLL_TYPE AUTO
QUALIFY_CONF_DONE
COMPENSATE_CLOCK CLK0
SCAN_CHAIN
GATE_LOCK_SIGNAL
GATE_LOCK_COUNTER
LOCK_HIGH
LOCK_LOW
VALID_LOCK_MULTIPLIER
INVALID_LOCK_MULTIPLIER
SWITCH_OVER_ON_LOSSCLK
SWITCH_OVER_ON_GATED_LOCK
ENABLE_SWITCH_OVER_COUNTER
SKIP_VCO
SWITCH_OVER_COUNTER
SWITCH_OVER_TYPE
FEEDBACK_SOURCE
BANDWIDTH
BANDWIDTH_TYPE AUTO
SPREAD_FREQUENCY
DOWN_SPREAD
SELF_RESET_ON_GATED_LOSS_LOCK
SELF_RESET_ON_LOSS_LOCK
CLK0_MULTIPLY_BY 5
CLK1_MULTIPLY_BY 1
CLK2_MULTIPLY_BY 1
CLK3_MULTIPLY_BY
CLK4_MULTIPLY_BY
CLK5_MULTIPLY_BY
CLK6_MULTIPLY_BY
CLK7_MULTIPLY_BY
CLK8_MULTIPLY_BY
CLK9_MULTIPLY_BY
EXTCLK0_MULTIPLY_BY
EXTCLK1_MULTIPLY_BY
EXTCLK2_MULTIPLY_BY
EXTCLK3_MULTIPLY_BY
CLK0_DIVIDE_BY 1
CLK1_DIVIDE_BY 2
CLK2_DIVIDE_BY 20
CLK3_DIVIDE_BY
CLK4_DIVIDE_BY
CLK5_DIVIDE_BY
CLK6_DIVIDE_BY
CLK7_DIVIDE_BY
CLK8_DIVIDE_BY
CLK9_DIVIDE_BY
EXTCLK0_DIVIDE_BY
EXTCLK1_DIVIDE_BY
EXTCLK2_DIVIDE_BY
EXTCLK3_DIVIDE_BY
CLK0_PHASE_SHIFT 0
CLK1_PHASE_SHIFT 15000
CLK2_PHASE_SHIFT 0
CLK3_PHASE_SHIFT
CLK4_PHASE_SHIFT
CLK5_PHASE_SHIFT
CLK6_PHASE_SHIFT
CLK7_PHASE_SHIFT
CLK8_PHASE_SHIFT
CLK9_PHASE_SHIFT
EXTCLK0_PHASE_SHIFT
EXTCLK1_PHASE_SHIFT
EXTCLK2_PHASE_SHIFT
EXTCLK3_PHASE_SHIFT
CLK0_DUTY_CYCLE 50
CLK1_DUTY_CYCLE 50
CLK2_DUTY_CYCLE 50
CLK3_DUTY_CYCLE
CLK4_DUTY_CYCLE
CLK5_DUTY_CYCLE
CLK6_DUTY_CYCLE
CLK7_DUTY_CYCLE
CLK8_DUTY_CYCLE
CLK9_DUTY_CYCLE
EXTCLK0_DUTY_CYCLE
EXTCLK1_DUTY_CYCLE
EXTCLK2_DUTY_CYCLE
EXTCLK3_DUTY_CYCLE
PORT_clkena0 PORT_UNUSED
PORT_clkena1 PORT_UNUSED
PORT_clkena2 PORT_UNUSED
PORT_clkena3 PORT_UNUSED
PORT_clkena4 PORT_UNUSED
PORT_clkena5 PORT_UNUSED
PORT_extclkena0
PORT_extclkena1
PORT_extclkena2
PORT_extclkena3
PORT_extclk0 PORT_UNUSED
PORT_extclk1 PORT_UNUSED
PORT_extclk2 PORT_UNUSED
PORT_extclk3 PORT_UNUSED
PORT_CLKBAD0 PORT_UNUSED
PORT_CLKBAD1 PORT_UNUSED
PORT_clk0 PORT_USED
PORT_clk1 PORT_UNUSED
PORT_clk2 PORT_UNUSED
PORT_clk3 PORT_UNUSED
PORT_clk4 PORT_UNUSED
PORT_clk5 PORT_UNUSED
PORT_clk6
PORT_clk7
PORT_clk8
PORT_clk9
PORT_SCANDATA PORT_UNUSED
PORT_SCANDATAOUT PORT_UNUSED
PORT_SCANDONE PORT_UNUSED
PORT_SCLKOUT1
PORT_SCLKOUT0
PORT_ACTIVECLOCK PORT_UNUSED
PORT_CLKLOSS PORT_UNUSED
PORT_INCLK1 PORT_UNUSED
PORT_INCLK0 PORT_USED
PORT_FBIN PORT_UNUSED
PORT_PLLENA PORT_UNUSED
PORT_CLKSWITCH PORT_UNUSED
PORT_ARESET PORT_USED
PORT_PFDENA PORT_UNUSED
PORT_SCANCLK PORT_UNUSED
PORT_SCANACLR PORT_UNUSED
PORT_SCANREAD PORT_UNUSED
PORT_SCANWRITE PORT_UNUSED
PORT_ENABLE0
PORT_ENABLE1
PORT_LOCKED PORT_USED
PORT_CONFIGUPDATE PORT_UNUSED
PORT_FBOUT
PORT_PHASEDONE PORT_UNUSED
PORT_PHASESTEP PORT_UNUSED
PORT_PHASEUPDOWN PORT_UNUSED
PORT_SCANCLKENA PORT_UNUSED
PORT_PHASECOUNTERSELECT PORT_UNUSED
PORT_VCOOVERRANGE
PORT_VCOUNDERRANGE
DPA_MULTIPLY_BY
DPA_DIVIDE_BY
DPA_DIVIDER
VCO_MULTIPLY_BY
VCO_DIVIDE_BY
SCLKOUT0_PHASE_SHIFT
SCLKOUT1_PHASE_SHIFT
VCO_FREQUENCY_CONTROL
VCO_PHASE_SHIFT_STEP
USING_FBMIMICBIDIR_PORT
SCAN_CHAIN_MIF_FILE
AVALON_USE_SEPARATE_SYSCLK NO
HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 15000 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 2 CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 0 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 135.00000000 PT#DIV_FACTOR2 20 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 2 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 250.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 5 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1423823783608952.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}
HIDDEN_IS_FIRST_EDIT 0
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

clock_bridge_0

altera_clock_bridge v15.0


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2_gen2 v15.0
sys_clk clk   cpu
  clk
clk_reset  
  reset
data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
debug_reset_request  
  reset
data_master   mem_if_ddr3_emif_0
  avl
instruction_master  
  avl
debug_reset_request  
  global_reset
debug_reset_request  
  soft_reset
data_master   ext_flash
  avl_csr
data_master  
  avl_mem
instruction_master  
  avl_csr
instruction_master  
  avl_mem
irq  
  interrupt_sender
debug_reset_request  
  reset
data_master   eth_tse
  control_port
debug_reset_request  
  reset_connection
data_master   sysid
  control_slave
debug_reset_request  
  reset
data_master   sgdma_tx
  csr
irq  
  csr_irq
debug_reset_request  
  reset
data_master   sgdma_rx
  csr
irq  
  csr_irq
debug_reset_request  
  reset
data_master   descriptor_memory
  s1
debug_reset_request  
  reset1
data_master   sys_clk_timer
  s1
irq  
  irq
debug_reset_request  
  reset
data_master   onchip_ram
  s1
debug_reset_request  
  reset1
data_master   led_pio
  s1
debug_reset_request  
  reset


Parameters

tmr_enabled false
setting_disable_tmr_inj false
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_preciseIllegalMemAccessException false
setting_exportPCB false
setting_exportdebuginfo false
setting_clearXBitsLDNonBypass true
setting_bigEndian false
setting_export_large_RAMs false
setting_asic_enabled false
setting_asic_synopsys_translate_on_off false
setting_asic_third_party_synthesis false
setting_asic_add_scan_mode_input false
setting_oci_version 1
setting_fast_register_read false
setting_exportHostDebugPort false
setting_oci_export_jtag_signals false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
io_regionbase 0
io_regionsize 0
setting_support31bitdcachebypass true
setting_activateTrace true
setting_allow_break_inst false
setting_activateTestEndChecker false
setting_ecc_sim_test_ports false
setting_disableocitrace false
setting_activateMonitors true
setting_HDLSimCachesCleared true
setting_HBreakTest false
setting_breakslaveoveride false
mpu_useLimit false
mpu_enabled false
mmu_enabled false
mmu_autoAssignTlbPtrSz true
cpuReset false
resetrequest_enabled true
setting_removeRAMinit false
setting_shadowRegisterSets 0
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mmu_TLBMissExcOffset 0
resetOffset 4390912
exceptionOffset 288
cpuID 0
breakOffset 32
userDefinedSettings
tracefilename
resetSlave ext_flash.avl_mem
mmu_TLBMissExcSlave
exceptionSlave mem_if_ddr3_emif_0.avl
breakSlave cpu.jtag_debug_module
setting_interruptControllerType Internal
setting_branchpredictiontype Dynamic
setting_bhtPtrSz 8
cpuArchRev 1
stratix_dspblock_shift_mul false
shifterType fast_le_shift
multiplierType mul_fast32
mul_shift_choice 0
mul_32_impl 3
mul_64_impl 0
shift_rot_impl 0
dividerType no_div
mpu_minInstRegionSize 12
mpu_minDataRegionSize 12
mmu_uitlbNumEntries 4
mmu_udtlbNumEntries 6
mmu_tlbPtrSz 7
mmu_tlbNumWays 16
mmu_processIDNumBits 8
impl Fast
icache_size 32768
fa_cache_line 2
fa_cache_linesize 0
icache_tagramBlockType Automatic
icache_ramBlockType Automatic
icache_numTCIM 0
icache_burstType None
dcache_bursts false
dcache_victim_buf_impl ram
dcache_size 32768
dcache_tagramBlockType Automatic
dcache_ramBlockType Automatic
dcache_numTCDM 0
setting_exportvectors false
setting_usedesignware false
setting_ecc_present false
setting_ic_ecc_present true
setting_rf_ecc_present true
setting_mmu_ecc_present true
setting_dc_ecc_present false
setting_itcm_ecc_present false
setting_dtcm_ecc_present false
regfile_ramBlockType Automatic
ocimem_ramBlockType Automatic
ocimem_ramInit false
mmu_ramBlockType Automatic
bht_ramBlockType Automatic
cdx_enabled false
mpx_enabled false
debug_enabled true
debug_triggerArming true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_jtagInstanceID 0
debug_OCIOnchipTrace _128
debug_hwbreakpoint 0
debug_datatrigger 0
debug_traceType none
debug_traceStorage onchip_trace
master_addr_map false
instruction_master_paddr_base 0
instruction_master_paddr_size 0
flash_instruction_master_paddr_base 0
flash_instruction_master_paddr_size 0
data_master_paddr_base 0
data_master_paddr_size 0
tightly_coupled_instruction_master_0_paddr_base 0
tightly_coupled_instruction_master_0_paddr_size 0
tightly_coupled_instruction_master_1_paddr_base 0
tightly_coupled_instruction_master_1_paddr_size 0
tightly_coupled_instruction_master_2_paddr_base 0
tightly_coupled_instruction_master_2_paddr_size 0
tightly_coupled_instruction_master_3_paddr_base 0
tightly_coupled_instruction_master_3_paddr_size 0
tightly_coupled_data_master_0_paddr_base 0
tightly_coupled_data_master_0_paddr_size 0
tightly_coupled_data_master_1_paddr_base 0
tightly_coupled_data_master_1_paddr_size 0
tightly_coupled_data_master_2_paddr_base 0
tightly_coupled_data_master_2_paddr_size 0
tightly_coupled_data_master_3_paddr_base 0
tightly_coupled_data_master_3_paddr_size 0
instruction_master_high_performance_paddr_base 0
instruction_master_high_performance_paddr_size 0
data_master_high_performance_paddr_base 0
data_master_high_performance_paddr_size 0
resetAbsoluteAddr 608370688
exceptionAbsoluteAddr 268435744
breakAbsoluteAddr 2099232
mmu_TLBMissExcAbsAddr 0
dcache_bursts_derived false
dcache_size_derived 32768
breakSlave_derived cpu.debug_mem_slave
dcache_lineSize_derived 32
setting_ioregionBypassDCache false
setting_bit31BypassDCache true
translate_on "synthesis translate_on"
translate_off "synthesis translate_off"
debug_onchiptrace false
debug_offchiptrace false
debug_insttrace false
debug_datatrace false
instAddrWidth 30
faAddrWidth 1
dataAddrWidth 30
tightlyCoupledDataMaster0AddrWidth 1
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster3AddrWidth 1
dataMasterHighPerformanceAddrWidth 1
instructionMasterHighPerformanceAddrWidth 1
instSlaveMapParam <address-map><slave name='cpu.debug_mem_slave' start='0x200800' end='0x201000' /><slave name='mem_if_ddr3_emif_0.avl' start='0x10000000' end='0x18000000' /><slave name='ext_flash.avl_csr' start='0x20000000' end='0x20000020' /><slave name='ext_flash.avl_mem' start='0x24000000' end='0x28000000' /></address-map>
faSlaveMapParam
dataSlaveMapParam <address-map><slave name='descriptor_memory.s1' start='0x0' end='0x2000' /><slave name='cpu.debug_mem_slave' start='0x200800' end='0x201000' /><slave name='eth_tse.control_port' start='0x201000' end='0x201400' /><slave name='sgdma_rx.csr' start='0x201600' end='0x201640' /><slave name='sgdma_tx.csr' start='0x201640' end='0x201680' /><slave name='sys_clk_timer.s1' start='0x201680' end='0x2016A0' /><slave name='jtag_uart.avalon_jtag_slave' start='0x2016B0' end='0x2016B8' /><slave name='sysid.control_slave' start='0x2016B8' end='0x2016C0' /><slave name='led_pio.s1' start='0x2016C0' end='0x2016D0' /><slave name='onchip_ram.s1' start='0x201800' end='0x202000' /><slave name='mem_if_ddr3_emif_0.avl' start='0x10000000' end='0x18000000' /><slave name='ext_flash.avl_csr' start='0x20000000' end='0x20000020' /><slave name='ext_flash.avl_mem' start='0x24000000' end='0x28000000' /></address-map>
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
dataMasterHighPerformanceMapParam
instructionMasterHighPerformanceMapParam
clockFrequency 50000000
deviceFamilyName MAX10FPGA
internalIrqMaskSystemInfo 47
customInstSlavesSystemInfo <info/>
customInstSlavesSystemInfo_nios_a <info/>
customInstSlavesSystemInfo_nios_b <info/>
customInstSlavesSystemInfo_nios_c <info/>
deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
AUTO_CLK_CLOCK_DOMAIN 13
AUTO_CLK_RESET_DOMAIN 13
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x00200820
CPU_ARCH_NIOS2_R1
CPU_FREQ 50000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 30
DCACHE_BYPASS_MASK 0x80000000
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 32768
EXCEPTION_ADDR 0x10000120
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_EXTRA_EXCEPTION_INFO
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 32768
INITDA_SUPPORTED
INST_ADDR_WIDTH 30
NUM_OF_SHADOW_REG_SETS 0
OCI_VERSION 1
RESET_ADDR 0x24430000

descriptor_memory

altera_avalon_onchip_memory2 v15.0
cpu data_master   descriptor_memory
  s1
debug_reset_request  
  reset1
sgdma_rx descriptor_read  
  s1
descriptor_write  
  s1
sgdma_tx descriptor_read  
  s1
descriptor_write  
  s1
sys_clk clk  
  clk1
clk_reset  
  reset1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName descriptor_memory
instanceID NONE
memorySize 8192
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
copyInitFile false
useShallowMemBlocks false
writable true
ecc_enabled false
resetrequest_enabled true
autoInitializationFileName q_sys_descriptor_memory
deviceFamily MAX10FPGA
deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width 11
derived_set_data_width 32
derived_gui_ram_block_type Automatic
derived_is_hardcopy false
derived_init_file_name q_sys_descriptor_memory.hex
generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE q_sys_descriptor_memory
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 8192
WRITABLE 1

enet_pll

altpll v15.0
sys_clk clk   enet_pll
  inclk_interface
mem_resetn out_reset  
  inclk_interface_reset


Parameters

HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY MAX 10
WIDTH_CLOCK 5
WIDTH_PHASECOUNTERSELECT
PRIMARY_CLOCK
INCLK0_INPUT_FREQUENCY 20000
INCLK1_INPUT_FREQUENCY
OPERATION_MODE NO_COMPENSATION
PLL_TYPE AUTO
QUALIFY_CONF_DONE
COMPENSATE_CLOCK CLK0
SCAN_CHAIN
GATE_LOCK_SIGNAL
GATE_LOCK_COUNTER
LOCK_HIGH
LOCK_LOW
VALID_LOCK_MULTIPLIER
INVALID_LOCK_MULTIPLIER
SWITCH_OVER_ON_LOSSCLK
SWITCH_OVER_ON_GATED_LOCK
ENABLE_SWITCH_OVER_COUNTER
SKIP_VCO
SWITCH_OVER_COUNTER
SWITCH_OVER_TYPE
FEEDBACK_SOURCE
BANDWIDTH
BANDWIDTH_TYPE AUTO
SPREAD_FREQUENCY
DOWN_SPREAD
SELF_RESET_ON_GATED_LOSS_LOCK
SELF_RESET_ON_LOSS_LOCK
CLK0_MULTIPLY_BY 5
CLK1_MULTIPLY_BY 1
CLK2_MULTIPLY_BY 1
CLK3_MULTIPLY_BY 5
CLK4_MULTIPLY_BY 1
CLK5_MULTIPLY_BY
CLK6_MULTIPLY_BY
CLK7_MULTIPLY_BY
CLK8_MULTIPLY_BY
CLK9_MULTIPLY_BY
EXTCLK0_MULTIPLY_BY
EXTCLK1_MULTIPLY_BY
EXTCLK2_MULTIPLY_BY
EXTCLK3_MULTIPLY_BY
CLK0_DIVIDE_BY 2
CLK1_DIVIDE_BY 2
CLK2_DIVIDE_BY 20
CLK3_DIVIDE_BY 2
CLK4_DIVIDE_BY 2
CLK5_DIVIDE_BY
CLK6_DIVIDE_BY
CLK7_DIVIDE_BY
CLK8_DIVIDE_BY
CLK9_DIVIDE_BY
EXTCLK0_DIVIDE_BY
EXTCLK1_DIVIDE_BY
EXTCLK2_DIVIDE_BY
EXTCLK3_DIVIDE_BY
CLK0_PHASE_SHIFT 0
CLK1_PHASE_SHIFT 0
CLK2_PHASE_SHIFT 0
CLK3_PHASE_SHIFT -3000
CLK4_PHASE_SHIFT -10000
CLK5_PHASE_SHIFT
CLK6_PHASE_SHIFT
CLK7_PHASE_SHIFT
CLK8_PHASE_SHIFT
CLK9_PHASE_SHIFT
EXTCLK0_PHASE_SHIFT
EXTCLK1_PHASE_SHIFT
EXTCLK2_PHASE_SHIFT
EXTCLK3_PHASE_SHIFT
CLK0_DUTY_CYCLE 50
CLK1_DUTY_CYCLE 50
CLK2_DUTY_CYCLE 50
CLK3_DUTY_CYCLE 50
CLK4_DUTY_CYCLE 50
CLK5_DUTY_CYCLE
CLK6_DUTY_CYCLE
CLK7_DUTY_CYCLE
CLK8_DUTY_CYCLE
CLK9_DUTY_CYCLE
EXTCLK0_DUTY_CYCLE
EXTCLK1_DUTY_CYCLE
EXTCLK2_DUTY_CYCLE
EXTCLK3_DUTY_CYCLE
PORT_clkena0 PORT_UNUSED
PORT_clkena1 PORT_UNUSED
PORT_clkena2 PORT_UNUSED
PORT_clkena3 PORT_UNUSED
PORT_clkena4 PORT_UNUSED
PORT_clkena5 PORT_UNUSED
PORT_extclkena0
PORT_extclkena1
PORT_extclkena2
PORT_extclkena3
PORT_extclk0 PORT_UNUSED
PORT_extclk1 PORT_UNUSED
PORT_extclk2 PORT_UNUSED
PORT_extclk3 PORT_UNUSED
PORT_CLKBAD0 PORT_UNUSED
PORT_CLKBAD1 PORT_UNUSED
PORT_clk0 PORT_USED
PORT_clk1 PORT_USED
PORT_clk2 PORT_USED
PORT_clk3 PORT_USED
PORT_clk4 PORT_USED
PORT_clk5 PORT_UNUSED
PORT_clk6
PORT_clk7
PORT_clk8
PORT_clk9
PORT_SCANDATA PORT_UNUSED
PORT_SCANDATAOUT PORT_UNUSED
PORT_SCANDONE PORT_UNUSED
PORT_SCLKOUT1
PORT_SCLKOUT0
PORT_ACTIVECLOCK PORT_UNUSED
PORT_CLKLOSS PORT_UNUSED
PORT_INCLK1 PORT_UNUSED
PORT_INCLK0 PORT_USED
PORT_FBIN PORT_UNUSED
PORT_PLLENA PORT_UNUSED
PORT_CLKSWITCH PORT_UNUSED
PORT_ARESET PORT_UNUSED
PORT_PFDENA PORT_UNUSED
PORT_SCANCLK PORT_UNUSED
PORT_SCANACLR PORT_UNUSED
PORT_SCANREAD PORT_UNUSED
PORT_SCANWRITE PORT_UNUSED
PORT_ENABLE0
PORT_ENABLE1
PORT_LOCKED PORT_USED
PORT_CONFIGUPDATE PORT_UNUSED
PORT_FBOUT
PORT_PHASEDONE PORT_UNUSED
PORT_PHASESTEP PORT_UNUSED
PORT_PHASEUPDOWN PORT_UNUSED
PORT_SCANCLKENA PORT_UNUSED
PORT_PHASECOUNTERSELECT PORT_UNUSED
PORT_VCOOVERRANGE
PORT_VCOUNDERRANGE
DPA_MULTIPLY_BY
DPA_DIVIDE_BY
DPA_DIVIDER
VCO_MULTIPLY_BY
VCO_DIVIDE_BY
SCLKOUT0_PHASE_SHIFT
SCLKOUT1_PHASE_SHIFT
VCO_FREQUENCY_CONTROL
VCO_PHASE_SHIFT_STEP
USING_FBMIMICBIDIR_PORT
SCAN_CHAIN_MIF_FILE
AVALON_USE_SEPARATE_SYSCLK NO
HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 20 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT -3000 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NO_COMPENSATION CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT -10000 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#CLK1_DIVIDE_BY 2 CT#CLK3_MULTIPLY_BY 5 CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 0 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 0 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 0 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 100.00000000 PT#OUTPUT_FREQ3 100.00000000 PT#OUTPUT_FREQ2 2.50000000 PT#OUTPUT_FREQ1 25.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 -90.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 -135.00000000 PT#DIV_FACTOR4 2 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 2 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 1 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 125.000000 PT#EFF_OUTPUT_FREQ_VALUE2 2.500000 PT#EFF_OUTPUT_FREQ_VALUE1 25.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 5 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1418882816093282.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}
HIDDEN_IS_FIRST_EDIT 0
AUTO_DEVICE_FAMILY MAX10FPGA
AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

(none)

eth_tse

altera_eth_tse v15.0
cpu data_master   eth_tse
  control_port
debug_reset_request  
  reset_connection
sgdma_tx out  
  transmit
sys_clk clk  
  control_port_clock_connection
clk  
  receive_clock_connection
clk  
  transmit_clock_connection
clk_reset  
  reset_connection
receive   sgdma_rx
  in


Parameters

deviceFamilyName MAX10FPGA
enable_padding true
enable_lgth_check true
gbit_only true
mbit_only true
reduced_control false
core_version 3840
dev_version 3840
eg_fifo 2048
ing_fifo 2048
reduced_interface_ena true
synchronizer_depth 3
deviceFamily MAX10
isUseMAC true
isUsePCS false
enable_clk_sharing false
core_variation MAC_ONLY
ifGMII RGMII
use_mac_clken false
enable_use_internal_fifo true
enable_ecc false
max_channels 1
use_misc_ports true
transceiver_type NONE
enable_hd_logic false
enable_gmii_loopback false
enable_sup_addr false
stat_cnt_ena true
ext_stat_cnt_ena false
ena_hash false
enable_shift16 true
enable_mac_flow_ctrl false
enable_mac_vlan false
enable_magic_detect true
useMDIO true
mdio_clk_div 40
enable_ena 32
eg_addr 11
ing_addr 11
phy_identifier 0
enable_sgmii true
export_pwrdn false
enable_alt_reconfig false
starting_channel_number 0
phyip_pll_type CMU
phyip_pll_base_data_rate 1250 Mbps
phyip_en_synce_support false
phyip_pma_bonding_mode x1
nf_phyip_rcfg_enable true
nf_lvds_iopll_num_channels 4
enable_timestamping false
enable_ptp_1step false
tstamp_fp_width 4
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
generateLegacySim false
  

Software Assignments

ENABLE_MACLITE 0
FIFO_WIDTH 32
IS_MULTICHANNEL_MAC 0
MACLITE_GIGE 0
MDIO_SHARED 0
NUMBER_OF_CHANNEL 1
NUMBER_OF_MAC_MDIO_SHARED 1
PCS 0
PCS_ID 0
PCS_SGMII 1
RECEIVE_FIFO_DEPTH 2048
REGISTER_SHARED 0
RGMII 1
TRANSMIT_FIFO_DEPTH 2048
USE_MDIO 1

ext_flash

altera_generic_quad_spi_controller v15.0
cpu data_master   ext_flash
  avl_csr
data_master  
  avl_mem
instruction_master  
  avl_csr
instruction_master  
  avl_mem
irq  
  interrupt_sender
debug_reset_request  
  reset
clock_bridge_0 out_clk  
  clock_sink
sys_clk clk_reset  
  reset


Parameters

DEVICE_FAMILY MAX10FPGA
CS_WIDTH 1
ADDR_WIDTH 24
ASI_WIDTH 4
ASMI_ADDR_WIDTH 32
ENABLE_4BYTE_ADDR 1
DDASI 1
FLASH_TYPE Micron512
IO_MODE QUAD
CHIP_SELS 1
deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

FLASH_TYPE Micron512
IS_EPCS 0
NUMBER_OF_SECTORS 1024
PAGE_SIZE 256
SECTOR_SIZE 65536
SUBSECTOR_SIZE 4096

jtag_uart

altera_avalon_jtag_uart v15.0
cpu data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
clkFreq 50000000
avalonSpec 2.0
legacySignalAllow false
enableInteractiveInput false
enableInteractiveOutput true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

led_pio

altera_avalon_pio v15.0
cpu data_master   led_pio
  s1
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 15
simDoTestBenchWiring false
simDrivenValue 0
width 4
clockRate 50000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 15

mem_if_ddr3_emif_0

altera_mem_if_ddr3_emif v15.0
cpu data_master   mem_if_ddr3_emif_0
  avl
instruction_master  
  avl
debug_reset_request  
  global_reset
debug_reset_request  
  soft_reset
sgdma_tx m_read  
  avl
sgdma_rx m_write  
  avl
sys_clk clk  
  pll_ref_clk
mem_resetn out_reset  
  global_reset
out_reset  
  soft_reset


Parameters

AC_ROM_MR0 0001000010001
AC_ROM_MR0_MIRR 0001000001001
AC_ROM_MR0_CALIB
AC_ROM_MR0_DLL_RESET 0001100010000
AC_ROM_MR0_DLL_RESET_MIRR 0001010001000
AC_ROM_MR1 0000000000000
AC_ROM_MR1_MIRR 0000000000000
AC_ROM_MR1_CALIB
AC_ROM_MR1_OCD_ENABLE
AC_ROM_MR2 0000000000000
AC_ROM_MR2_MIRR 0000000000000
AC_ROM_MR3 0000000000000
AC_ROM_MR3_MIRR 0000000000000
USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY false
MR0_BL 1
MR0_BT 0
MR0_CAS_LATENCY 1
MR0_DLL 1
MR0_WR 1
MR0_PD 0
MR1_DLL 0
MR1_ODS 0
MR1_RTT 0
MR1_AL 0
MR1_WL 0
MR1_TDQS 0
MR1_QOFF 0
MR1_DQS 0
MR1_RDQS 0
MR2_CWL 0
MR2_ASR 0
MR2_SRT 0
MR2_SRF 0
MR2_RTT_WR 0
MR3_MPR_RF 0
MR3_MPR 0
MR3_MPR_AA 0
MEM_IF_READ_DQS_WIDTH 1
MEM_IF_WRITE_DQS_WIDTH 1
SCC_DATA_WIDTH 1
MEM_IF_ADDR_WIDTH 14
MEM_IF_ADDR_WIDTH_MIN 13
MEM_IF_ROW_ADDR_WIDTH 14
MEM_IF_COL_ADDR_WIDTH 10
MEM_IF_DM_WIDTH 1
MEM_IF_CS_PER_RANK 1
MEM_IF_NUMBER_OF_RANKS 1
MEM_IF_CS_PER_DIMM 1
MEM_IF_CONTROL_WIDTH 1
MEM_BURST_LENGTH 8
MEM_LEVELING true
MEM_IF_DQS_WIDTH 1
MEM_IF_CS_WIDTH 1
MEM_IF_CHIP_BITS 1
MEM_IF_BANKADDR_WIDTH 3
MEM_IF_DQ_WIDTH 8
MEM_IF_CK_WIDTH 1
MEM_IF_CLK_EN_WIDTH 1
MEM_IF_CLK_PAIR_COUNT 1
DEVICE_WIDTH 1
MEM_CLK_MAX_NS 1.25
MEM_CLK_MAX_PS 1250.0
MEM_TRC 15
MEM_TRAS 11
MEM_TRCD 5
MEM_TRP 5
MEM_TREFI 2341
MEM_TRFC 34
CFG_TCCD 1
MEM_TWR 5
MEM_TFAW 10
MEM_TRRD 2
MEM_TRTP 3
MEM_DQS_TO_CLK_CAPTURE_DELAY 100
MEM_CLK_TO_DQS_CAPTURE_DELAY 100000
MEM_IF_ODT_WIDTH 1
MEM_WTCL_INT 5
FLY_BY false
RDIMM false
LRDIMM false
RDIMM_INT 0
LRDIMM_INT 0
MEM_IF_LRDIMM_RM 0
MEM_IF_RD_TO_WR_TURNAROUND_OCT 2
MEM_IF_WR_TO_RD_TURNAROUND_OCT 3
CTL_RD_TO_PCH_EXTRA_CLK 0
CTL_RD_TO_RD_EXTRA_CLK 0
CTL_WR_TO_WR_EXTRA_CLK 0
CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1
CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 1
MEM_TYPE DDR3
MEM_MIRROR_ADDRESSING_DEC 0
MEM_ATCL_INT 0
MEM_REGDIMM_ENABLED false
MEM_LRDIMM_ENABLED false
MEM_VENDOR JEDEC
MEM_FORMAT DISCRETE
AC_PARITY false
RDIMM_CONFIG 0000000000000000
LRDIMM_EXTENDED_CONFIG 0x000000000000000000
DISCRETE_FLY_BY true
DEVICE_DEPTH 1
MEM_MIRROR_ADDRESSING 0
MEM_CLK_FREQ_MAX 800.0
MEM_ROW_ADDR_WIDTH 14
MEM_COL_ADDR_WIDTH 10
MEM_DQ_WIDTH 8
MEM_DQ_PER_DQS 8
MEM_BANKADDR_WIDTH 3
MEM_IF_DM_PINS_EN true
MEM_IF_DQSN_EN true
MEM_NUMBER_OF_DIMMS 1
MEM_NUMBER_OF_RANKS_PER_DIMM 1
MEM_NUMBER_OF_RANKS_PER_DEVICE 1
MEM_RANK_MULTIPLICATION_FACTOR 1
MEM_CK_WIDTH 1
MEM_CS_WIDTH 1
MEM_CLK_EN_WIDTH 1
ALTMEMPHY_COMPATIBLE_MODE false
NEXTGEN true
MEM_IF_BOARD_BASE_DELAY 10
MEM_IF_SIM_VALID_WINDOW 0
MEM_GUARANTEED_WRITE_INIT false
MEM_VERBOSE true
PINGPONGPHY_EN false
DUPLICATE_AC false
REFRESH_BURST_VALIDATION false
AP_MODE_EN 0
AP_MODE false
MEM_BL OTF
MEM_BT Sequential
MEM_ASR Manual
MEM_SRT Normal
MEM_PD DLL off
MEM_DRV_STR RZQ/6
MEM_DLL_EN true
MEM_RTT_NOM ODT Disabled
MEM_RTT_WR Dynamic ODT off
MEM_WTCL 5
MEM_ATCL Disabled
MEM_TCL 5
MEM_AUTO_LEVELING_MODE true
MEM_USER_LEVELING_MODE Leveling
MEM_INIT_EN false
MEM_INIT_FILE
DAT_DATA_WIDTH 32
TIMING_TIS 170
TIMING_TIH 120
TIMING_TDS 10
TIMING_TDH 45
TIMING_TDQSQ 100
TIMING_TQH 0.38
TIMING_TDQSCK 225
TIMING_TDQSCKDS 450
TIMING_TDQSCKDM 900
TIMING_TDQSCKDL 1200
TIMING_TDQSS 0.27
TIMING_TQSH 0.4
TIMING_TDSH 0.18
TIMING_TDSS 0.18
MEM_TINIT_US 500
MEM_TINIT_CK 150000
MEM_TDQSCK 1
MEM_TMRD_CK 4
MEM_TRAS_NS 35.0
MEM_TRCD_NS 13.75
MEM_TRP_NS 13.75
MEM_TREFI_US 7.8
MEM_TRFC_NS 110.0
CFG_TCCD_NS 2.5
MEM_TWR_NS 15.0
MEM_TWTR 6
MEM_TFAW_NS 30.0
MEM_TRRD_NS 6.0
MEM_TRTP_NS 7.5
RATE Half
MEM_CLK_FREQ 300.0
USE_MEM_CLK_FREQ false
USE_DQS_TRACKING false
FORCE_DQS_TRACKING AUTO
USE_HPS_DQS_TRACKING false
TRK_PARALLEL_SCC_LOAD false
USE_SHADOW_REGS false
FORCE_SHADOW_REGS AUTO
DQ_DDR 1
ADDR_CMD_DDR 0
AFI_RATE_RATIO 2
DATA_RATE_RATIO 2
ADDR_RATE_RATIO 1
AFI_ADDR_WIDTH 28
AFI_BANKADDR_WIDTH 6
AFI_CONTROL_WIDTH 2
AFI_CS_WIDTH 2
AFI_CLK_EN_WIDTH 2
AFI_DM_WIDTH 4
AFI_DQ_WIDTH 32
AFI_ODT_WIDTH 2
AFI_WRITE_DQS_WIDTH 2
AFI_RLAT_WIDTH 6
AFI_WLAT_WIDTH 6
AFI_RRANK_WIDTH 2
AFI_WRANK_WIDTH 2
AFI_CLK_PAIR_COUNT 1
MRS_MIRROR_PING_PONG_ATSO false
SYS_INFO_DEVICE_FAMILY MAX10FPGA
PARSE_FRIENDLY_DEVICE_FAMILY MAX10
DEVICE_FAMILY MAX 10
PRE_V_SERIES_FAMILY true
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM
DEVICE_FAMILY_PARAM
SPEED_GRADE 6
IS_ES_DEVICE false
DISABLE_CHILD_MESSAGING false
HARD_PHY false
HARD_EMIF false
HHP_HPS false
HHP_HPS_VERIFICATION false
HHP_HPS_SIMULATION false
HPS_PROTOCOL DEFAULT
CUT_NEW_FAMILY_TIMING true
EXPORT_CSR_PORT false
CSR_ADDR_WIDTH 8
CSR_DATA_WIDTH 32
CSR_BE_WIDTH 4
CTL_CS_WIDTH 1
AVL_ADDR_WIDTH 25
AVL_BE_WIDTH 4
AVL_DATA_WIDTH 32
AVL_SYMBOL_WIDTH 8
AVL_NUM_SYMBOLS 4
AVL_SIZE_WIDTH 3
HR_DDIO_OUT_HAS_THREE_REGS false
CTL_ECC_CSR_ENABLED false
DWIDTH_RATIO 4
CTL_ODT_ENABLED false
CTL_OUTPUT_REGD false
CTL_ECC_MULTIPLES_40_72 1
CTL_ECC_MULTIPLES_16_24_40_72 1
CTL_REGDIMM_ENABLED false
LOW_LATENCY false
CONTROLLER_TYPE nextgen_v110
CTL_TBP_NUM 4
CTL_USR_REFRESH 0
CTL_SELF_REFRESH 0
CFG_TYPE 2
CFG_INTERFACE_WIDTH 8
CFG_BURST_LENGTH 8
CFG_ADDR_ORDER 0
CFG_PDN_EXIT_CYCLES 10
CFG_POWER_SAVING_EXIT_CYCLES 5
CFG_MEM_CLK_ENTRY_CYCLES 20
CFG_SELF_RFSH_EXIT_CYCLES 512
CFG_PORT_WIDTH_WRITE_ODT_CHIP 1
CFG_PORT_WIDTH_READ_ODT_CHIP 1
CFG_WRITE_ODT_CHIP 1
CFG_READ_ODT_CHIP 0
LOCAL_CS_WIDTH 0
CFG_CLR_INTR 0
CFG_ENABLE_NO_DM 0
MEM_ADD_LAT 0
CTL_ENABLE_BURST_INTERRUPT_INT false
CTL_ENABLE_BURST_TERMINATE_INT false
CFG_ERRCMD_FIFO_REG 0
CFG_ECC_DECODER_REG 0
CTL_ENABLE_WDATA_PATH_LATENCY false
CFG_STARVE_LIMIT 10
MEM_AUTO_PD_CYCLES 0
AVL_PORT
AVL_DATA_WIDTH_PORT_0 0
AVL_ADDR_WIDTH_PORT_0 0
PRIORITY_PORT_0 0
WEIGHT_PORT_0 0
CPORT_TYPE_PORT_0 0
AVL_NUM_SYMBOLS_PORT_0 2
LSB_WFIFO_PORT_0 5
MSB_WFIFO_PORT_0 5
LSB_RFIFO_PORT_0 5
MSB_RFIFO_PORT_0 5
AVL_DATA_WIDTH_PORT_1 0
AVL_ADDR_WIDTH_PORT_1 0
PRIORITY_PORT_1 0
WEIGHT_PORT_1 0
CPORT_TYPE_PORT_1 0
AVL_NUM_SYMBOLS_PORT_1 2
LSB_WFIFO_PORT_1 5
MSB_WFIFO_PORT_1 5
LSB_RFIFO_PORT_1 5
MSB_RFIFO_PORT_1 5
AVL_DATA_WIDTH_PORT_2 0
AVL_ADDR_WIDTH_PORT_2 0
PRIORITY_PORT_2 0
WEIGHT_PORT_2 0
CPORT_TYPE_PORT_2 0
AVL_NUM_SYMBOLS_PORT_2 2
LSB_WFIFO_PORT_2 5
MSB_WFIFO_PORT_2 5
LSB_RFIFO_PORT_2 5
MSB_RFIFO_PORT_2 5
AVL_DATA_WIDTH_PORT_3 0
AVL_ADDR_WIDTH_PORT_3 0
PRIORITY_PORT_3 0
WEIGHT_PORT_3 0
CPORT_TYPE_PORT_3 0
AVL_NUM_SYMBOLS_PORT_3 2
LSB_WFIFO_PORT_3 5
MSB_WFIFO_PORT_3 5
LSB_RFIFO_PORT_3 5
MSB_RFIFO_PORT_3 5
AVL_DATA_WIDTH_PORT_4 0
AVL_ADDR_WIDTH_PORT_4 0
PRIORITY_PORT_4 0
WEIGHT_PORT_4 0
CPORT_TYPE_PORT_4 0
AVL_NUM_SYMBOLS_PORT_4 2
LSB_WFIFO_PORT_4 5
MSB_WFIFO_PORT_4 5
LSB_RFIFO_PORT_4 5
MSB_RFIFO_PORT_4 5
AVL_DATA_WIDTH_PORT_5 0
AVL_ADDR_WIDTH_PORT_5 0
PRIORITY_PORT_5 0
WEIGHT_PORT_5 0
CPORT_TYPE_PORT_5 0
AVL_NUM_SYMBOLS_PORT_5 2
LSB_WFIFO_PORT_5 5
MSB_WFIFO_PORT_5 5
LSB_RFIFO_PORT_5 5
MSB_RFIFO_PORT_5 5
ALLOCATED_RFIFO_PORT 0,None,None,None,None,None
ALLOCATED_WFIFO_PORT 0,None,None,None,None,None
ENUM_ATTR_COUNTER_ONE_RESET DISABLED
ENUM_ATTR_COUNTER_ZERO_RESET DISABLED
ENUM_ATTR_STATIC_CONFIG_VALID DISABLED
ENUM_AUTO_PCH_ENABLE_0 DISABLED
ENUM_AUTO_PCH_ENABLE_1 DISABLED
ENUM_AUTO_PCH_ENABLE_2 DISABLED
ENUM_AUTO_PCH_ENABLE_3 DISABLED
ENUM_AUTO_PCH_ENABLE_4 DISABLED
ENUM_AUTO_PCH_ENABLE_5 DISABLED
ENUM_CAL_REQ DISABLED
ENUM_CFG_BURST_LENGTH BL_8
ENUM_CFG_INTERFACE_WIDTH DWIDTH_32
ENUM_CFG_SELF_RFSH_EXIT_CYCLES
ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_32
ENUM_CFG_TYPE DDR3
ENUM_CLOCK_OFF_0 DISABLED
ENUM_CLOCK_OFF_1 DISABLED
ENUM_CLOCK_OFF_2 DISABLED
ENUM_CLOCK_OFF_3 DISABLED
ENUM_CLOCK_OFF_4 DISABLED
ENUM_CLOCK_OFF_5 DISABLED
ENUM_CLR_INTR NO_CLR_INTR
ENUM_CMD_PORT_IN_USE_0 FALSE
ENUM_CMD_PORT_IN_USE_1 FALSE
ENUM_CMD_PORT_IN_USE_2 FALSE
ENUM_CMD_PORT_IN_USE_3 FALSE
ENUM_CMD_PORT_IN_USE_4 FALSE
ENUM_CMD_PORT_IN_USE_5 FALSE
ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT0_RFIFO_MAP FIFO_0
ENUM_CPORT0_TYPE DISABLE
ENUM_CPORT0_WFIFO_MAP FIFO_0
ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT1_RFIFO_MAP FIFO_0
ENUM_CPORT1_TYPE DISABLE
ENUM_CPORT1_WFIFO_MAP FIFO_0
ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT2_RFIFO_MAP FIFO_0
ENUM_CPORT2_TYPE DISABLE
ENUM_CPORT2_WFIFO_MAP FIFO_0
ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT3_RFIFO_MAP FIFO_0
ENUM_CPORT3_TYPE DISABLE
ENUM_CPORT3_WFIFO_MAP FIFO_0
ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT4_RFIFO_MAP FIFO_0
ENUM_CPORT4_TYPE DISABLE
ENUM_CPORT4_WFIFO_MAP FIFO_0
ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT5_RFIFO_MAP FIFO_0
ENUM_CPORT5_TYPE DISABLE
ENUM_CPORT5_WFIFO_MAP FIFO_0
ENUM_CTL_ADDR_ORDER CHIP_BANK_ROW_COL
ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED
ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED
ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED
ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED
ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT
ENUM_DELAY_BONDING BONDING_LATENCY_0
ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED
ENUM_DISABLE_MERGING MERGING_ENABLED
ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0
ENUM_ENABLE_ATPG DISABLED
ENUM_ENABLE_BONDING_0 DISABLED
ENUM_ENABLE_BONDING_1 DISABLED
ENUM_ENABLE_BONDING_2 DISABLED
ENUM_ENABLE_BONDING_3 DISABLED
ENUM_ENABLE_BONDING_4 DISABLED
ENUM_ENABLE_BONDING_5 DISABLED
ENUM_ENABLE_BONDING_WRAPBACK DISABLED
ENUM_ENABLE_DQS_TRACKING DISABLED
ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED
ENUM_ENABLE_FAST_EXIT_PPD DISABLED
ENUM_ENABLE_INTR DISABLED
ENUM_ENABLE_NO_DM DISABLED
ENUM_ENABLE_PIPELINEGLOBAL DISABLED
ENUM_GANGED_ARF DISABLED
ENUM_GEN_DBE GEN_DBE_DISABLED
ENUM_GEN_SBE GEN_SBE_DISABLED
ENUM_INC_SYNC FIFO_SET_2
ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_2
ENUM_MASK_CORR_DROPPED_INTR DISABLED
ENUM_MASK_DBE_INTR DISABLED
ENUM_MASK_SBE_INTR DISABLED
ENUM_MEM_IF_AL AL_0
ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3
ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8
ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_12
ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1
ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1
ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8
ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4
ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32
ENUM_MEM_IF_MEMTYPE DDR3_SDRAM
ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_16
ENUM_MEM_IF_SPEEDBIN DDR3_1066_6_6_6
ENUM_MEM_IF_TCCD TCCD_4
ENUM_MEM_IF_TCL TCL_6
ENUM_MEM_IF_TCWL TCWL_5
ENUM_MEM_IF_TFAW TFAW_16
ENUM_MEM_IF_TMRD
ENUM_MEM_IF_TRAS TRAS_16
ENUM_MEM_IF_TRC TRC_22
ENUM_MEM_IF_TRCD TRCD_6
ENUM_MEM_IF_TRP TRP_6
ENUM_MEM_IF_TRRD TRRD_4
ENUM_MEM_IF_TRTP TRTP_4
ENUM_MEM_IF_TWR TWR_6
ENUM_MEM_IF_TWTR TWTR_4
ENUM_MMR_CFG_MEM_BL MP_BL_8
ENUM_OUTPUT_REGD DISABLED
ENUM_PDN_EXIT_CYCLES SLOW_EXIT
ENUM_PORT0_WIDTH PORT_64_BIT
ENUM_PORT1_WIDTH PORT_64_BIT
ENUM_PORT2_WIDTH PORT_64_BIT
ENUM_PORT3_WIDTH PORT_64_BIT
ENUM_PORT4_WIDTH PORT_64_BIT
ENUM_PORT5_WIDTH PORT_64_BIT
ENUM_PRIORITY_0_0 WEIGHT_0
ENUM_PRIORITY_0_1 WEIGHT_0
ENUM_PRIORITY_0_2 WEIGHT_0
ENUM_PRIORITY_0_3 WEIGHT_0
ENUM_PRIORITY_0_4 WEIGHT_0
ENUM_PRIORITY_0_5 WEIGHT_0
ENUM_PRIORITY_1_0 WEIGHT_0
ENUM_PRIORITY_1_1 WEIGHT_0
ENUM_PRIORITY_1_2 WEIGHT_0
ENUM_PRIORITY_1_3 WEIGHT_0
ENUM_PRIORITY_1_4 WEIGHT_0
ENUM_PRIORITY_1_5 WEIGHT_0
ENUM_PRIORITY_2_0 WEIGHT_0
ENUM_PRIORITY_2_1 WEIGHT_0
ENUM_PRIORITY_2_2 WEIGHT_0
ENUM_PRIORITY_2_3 WEIGHT_0
ENUM_PRIORITY_2_4 WEIGHT_0
ENUM_PRIORITY_2_5 WEIGHT_0
ENUM_PRIORITY_3_0 WEIGHT_0
ENUM_PRIORITY_3_1 WEIGHT_0
ENUM_PRIORITY_3_2 WEIGHT_0
ENUM_PRIORITY_3_3 WEIGHT_0
ENUM_PRIORITY_3_4 WEIGHT_0
ENUM_PRIORITY_3_5 WEIGHT_0
ENUM_PRIORITY_4_0 WEIGHT_0
ENUM_PRIORITY_4_1 WEIGHT_0
ENUM_PRIORITY_4_2 WEIGHT_0
ENUM_PRIORITY_4_3 WEIGHT_0
ENUM_PRIORITY_4_4 WEIGHT_0
ENUM_PRIORITY_4_5 WEIGHT_0
ENUM_PRIORITY_5_0 WEIGHT_0
ENUM_PRIORITY_5_1 WEIGHT_0
ENUM_PRIORITY_5_2 WEIGHT_0
ENUM_PRIORITY_5_3 WEIGHT_0
ENUM_PRIORITY_5_4 WEIGHT_0
ENUM_PRIORITY_5_5 WEIGHT_0
ENUM_PRIORITY_6_0 WEIGHT_0
ENUM_PRIORITY_6_1 WEIGHT_0
ENUM_PRIORITY_6_2 WEIGHT_0
ENUM_PRIORITY_6_3 WEIGHT_0
ENUM_PRIORITY_6_4 WEIGHT_0
ENUM_PRIORITY_6_5 WEIGHT_0
ENUM_PRIORITY_7_0 WEIGHT_0
ENUM_PRIORITY_7_1 WEIGHT_0
ENUM_PRIORITY_7_2 WEIGHT_0
ENUM_PRIORITY_7_3 WEIGHT_0
ENUM_PRIORITY_7_4 WEIGHT_0
ENUM_PRIORITY_7_5 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0
ENUM_RCFG_USER_PRIORITY_0 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_1 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_2 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_3 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_4 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_5 PRIORITY_0
ENUM_RD_DWIDTH_0 DWIDTH_0
ENUM_RD_DWIDTH_1 DWIDTH_0
ENUM_RD_DWIDTH_2 DWIDTH_0
ENUM_RD_DWIDTH_3 DWIDTH_0
ENUM_RD_DWIDTH_4 DWIDTH_0
ENUM_RD_DWIDTH_5 DWIDTH_0
ENUM_RD_FIFO_IN_USE_0 FALSE
ENUM_RD_FIFO_IN_USE_1 FALSE
ENUM_RD_FIFO_IN_USE_2 FALSE
ENUM_RD_FIFO_IN_USE_3 FALSE
ENUM_RD_PORT_INFO_0 USE_NO
ENUM_RD_PORT_INFO_1 USE_NO
ENUM_RD_PORT_INFO_2 USE_NO
ENUM_RD_PORT_INFO_3 USE_NO
ENUM_RD_PORT_INFO_4 USE_NO
ENUM_RD_PORT_INFO_5 USE_NO
ENUM_READ_ODT_CHIP ODT_DISABLED
ENUM_REORDER_DATA DATA_REORDERING
ENUM_RFIFO0_CPORT_MAP CMD_PORT_0
ENUM_RFIFO1_CPORT_MAP CMD_PORT_0
ENUM_RFIFO2_CPORT_MAP CMD_PORT_0
ENUM_RFIFO3_CPORT_MAP CMD_PORT_0
ENUM_SINGLE_READY_0 CONCATENATE_RDY
ENUM_SINGLE_READY_1 CONCATENATE_RDY
ENUM_SINGLE_READY_2 CONCATENATE_RDY
ENUM_SINGLE_READY_3 CONCATENATE_RDY
ENUM_STATIC_WEIGHT_0 WEIGHT_0
ENUM_STATIC_WEIGHT_1 WEIGHT_0
ENUM_STATIC_WEIGHT_2 WEIGHT_0
ENUM_STATIC_WEIGHT_3 WEIGHT_0
ENUM_STATIC_WEIGHT_4 WEIGHT_0
ENUM_STATIC_WEIGHT_5 WEIGHT_0
ENUM_SYNC_MODE_0 ASYNCHRONOUS
ENUM_SYNC_MODE_1 ASYNCHRONOUS
ENUM_SYNC_MODE_2 ASYNCHRONOUS
ENUM_SYNC_MODE_3 ASYNCHRONOUS
ENUM_SYNC_MODE_4 ASYNCHRONOUS
ENUM_SYNC_MODE_5 ASYNCHRONOUS
ENUM_TEST_MODE NORMAL_MODE
ENUM_THLD_JAR1_0 THRESHOLD_32
ENUM_THLD_JAR1_1 THRESHOLD_32
ENUM_THLD_JAR1_2 THRESHOLD_32
ENUM_THLD_JAR1_3 THRESHOLD_32
ENUM_THLD_JAR1_4 THRESHOLD_32
ENUM_THLD_JAR1_5 THRESHOLD_32
ENUM_THLD_JAR2_0 THRESHOLD_16
ENUM_THLD_JAR2_1 THRESHOLD_16
ENUM_THLD_JAR2_2 THRESHOLD_16
ENUM_THLD_JAR2_3 THRESHOLD_16
ENUM_THLD_JAR2_4 THRESHOLD_16
ENUM_THLD_JAR2_5 THRESHOLD_16
ENUM_USE_ALMOST_EMPTY_0 EMPTY
ENUM_USE_ALMOST_EMPTY_1 EMPTY
ENUM_USE_ALMOST_EMPTY_2 EMPTY
ENUM_USE_ALMOST_EMPTY_3 EMPTY
ENUM_USER_ECC_EN DISABLE
ENUM_USER_PRIORITY_0 PRIORITY_0
ENUM_USER_PRIORITY_1 PRIORITY_0
ENUM_USER_PRIORITY_2 PRIORITY_0
ENUM_USER_PRIORITY_3 PRIORITY_0
ENUM_USER_PRIORITY_4 PRIORITY_0
ENUM_USER_PRIORITY_5 PRIORITY_0
ENUM_WFIFO0_CPORT_MAP CMD_PORT_0
ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO1_CPORT_MAP CMD_PORT_0
ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO2_CPORT_MAP CMD_PORT_0
ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO3_CPORT_MAP CMD_PORT_0
ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL
ENUM_WR_DWIDTH_0 DWIDTH_0
ENUM_WR_DWIDTH_1 DWIDTH_0
ENUM_WR_DWIDTH_2 DWIDTH_0
ENUM_WR_DWIDTH_3 DWIDTH_0
ENUM_WR_DWIDTH_4 DWIDTH_0
ENUM_WR_DWIDTH_5 DWIDTH_0
ENUM_WR_FIFO_IN_USE_0 FALSE
ENUM_WR_FIFO_IN_USE_1 FALSE
ENUM_WR_FIFO_IN_USE_2 FALSE
ENUM_WR_FIFO_IN_USE_3 FALSE
ENUM_WR_PORT_INFO_0 USE_NO
ENUM_WR_PORT_INFO_1 USE_NO
ENUM_WR_PORT_INFO_2 USE_NO
ENUM_WR_PORT_INFO_3 USE_NO
ENUM_WR_PORT_INFO_4 USE_NO
ENUM_WR_PORT_INFO_5 USE_NO
ENUM_WRITE_ODT_CHIP ODT_DISABLED
INTG_MEM_AUTO_PD_CYCLES 0
INTG_CYC_TO_RLD_JARS_0 1
INTG_CYC_TO_RLD_JARS_1 1
INTG_CYC_TO_RLD_JARS_2 1
INTG_CYC_TO_RLD_JARS_3 1
INTG_CYC_TO_RLD_JARS_4 1
INTG_CYC_TO_RLD_JARS_5 1
INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0
INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0
INTG_EXTRA_CTL_CLK_ARF_PERIOD 0
INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0
INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0
INTG_EXTRA_CTL_CLK_PDN_PERIOD 0
INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0
INTG_EXTRA_CTL_CLK_RD_TO_PCH 0
INTG_EXTRA_CTL_CLK_RD_TO_RD 0
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_RD_TO_WR 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0
INTG_EXTRA_CTL_CLK_WR_TO_PCH 0
INTG_EXTRA_CTL_CLK_WR_TO_RD 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_WR_TO_WR 0
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0
INTG_MEM_IF_TREFI 3120
INTG_MEM_IF_TRFC 34
INTG_RCFG_SUM_WT_PRIORITY_0 0
INTG_RCFG_SUM_WT_PRIORITY_1 0
INTG_RCFG_SUM_WT_PRIORITY_2 0
INTG_RCFG_SUM_WT_PRIORITY_3 0
INTG_RCFG_SUM_WT_PRIORITY_4 0
INTG_RCFG_SUM_WT_PRIORITY_5 0
INTG_RCFG_SUM_WT_PRIORITY_6 0
INTG_RCFG_SUM_WT_PRIORITY_7 0
INTG_SUM_WT_PRIORITY_0 0
INTG_SUM_WT_PRIORITY_1 0
INTG_SUM_WT_PRIORITY_2 0
INTG_SUM_WT_PRIORITY_3 0
INTG_SUM_WT_PRIORITY_4 0
INTG_SUM_WT_PRIORITY_5 0
INTG_SUM_WT_PRIORITY_6 0
INTG_SUM_WT_PRIORITY_7 0
VECT_ATTR_COUNTER_ONE_MASK 0
VECT_ATTR_COUNTER_ONE_MATCH 0
VECT_ATTR_COUNTER_ZERO_MASK 0
VECT_ATTR_COUNTER_ZERO_MATCH 0
VECT_ATTR_DEBUG_SELECT_BYTE 0
INTG_POWER_SAVING_EXIT_CYCLES 5
INTG_MEM_CLK_ENTRY_CYCLES 10
ENUM_ENABLE_BURST_INTERRUPT DISABLED
ENUM_ENABLE_BURST_TERMINATE DISABLED
AV_PORT_0_CONNECT_TO_CV_PORT 0
CV_PORT_0_CONNECT_TO_AV_PORT 0
CV_AVL_DATA_WIDTH_PORT_0 0
CV_AVL_ADDR_WIDTH_PORT_0 0
CV_CPORT_TYPE_PORT_0 0
CV_AVL_NUM_SYMBOLS_PORT_0 2
CV_LSB_WFIFO_PORT_0 5
CV_MSB_WFIFO_PORT_0 5
CV_LSB_RFIFO_PORT_0 5
CV_MSB_RFIFO_PORT_0 5
CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED
CV_ENUM_CMD_PORT_IN_USE_0 FALSE
CV_ENUM_CPORT0_RFIFO_MAP FIFO_0
CV_ENUM_CPORT0_TYPE DISABLE
CV_ENUM_CPORT0_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_0 DISABLED
CV_ENUM_PORT0_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_0 WEIGHT_0
CV_ENUM_PRIORITY_1_0 WEIGHT_0
CV_ENUM_PRIORITY_2_0 WEIGHT_0
CV_ENUM_PRIORITY_3_0 WEIGHT_0
CV_ENUM_PRIORITY_4_0 WEIGHT_0
CV_ENUM_PRIORITY_5_0 WEIGHT_0
CV_ENUM_PRIORITY_6_0 WEIGHT_0
CV_ENUM_PRIORITY_7_0 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_0
CV_ENUM_RD_DWIDTH_0 DWIDTH_0
CV_ENUM_RD_PORT_INFO_0 USE_NO
CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0
CV_ENUM_USER_PRIORITY_0 PRIORITY_0
CV_ENUM_WR_DWIDTH_0 DWIDTH_0
CV_ENUM_WR_PORT_INFO_0 USE_NO
TG_TEMP_PORT_0 0
AV_PORT_1_CONNECT_TO_CV_PORT 1
CV_PORT_1_CONNECT_TO_AV_PORT 1
CV_AVL_DATA_WIDTH_PORT_1 0
CV_AVL_ADDR_WIDTH_PORT_1 0
CV_CPORT_TYPE_PORT_1 0
CV_AVL_NUM_SYMBOLS_PORT_1 2
CV_LSB_WFIFO_PORT_1 5
CV_MSB_WFIFO_PORT_1 5
CV_LSB_RFIFO_PORT_1 5
CV_MSB_RFIFO_PORT_1 5
CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED
CV_ENUM_CMD_PORT_IN_USE_1 FALSE
CV_ENUM_CPORT1_RFIFO_MAP FIFO_0
CV_ENUM_CPORT1_TYPE DISABLE
CV_ENUM_CPORT1_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_1 DISABLED
CV_ENUM_PORT1_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_1 WEIGHT_0
CV_ENUM_PRIORITY_1_1 WEIGHT_0
CV_ENUM_PRIORITY_2_1 WEIGHT_0
CV_ENUM_PRIORITY_3_1 WEIGHT_0
CV_ENUM_PRIORITY_4_1 WEIGHT_0
CV_ENUM_PRIORITY_5_1 WEIGHT_0
CV_ENUM_PRIORITY_6_1 WEIGHT_0
CV_ENUM_PRIORITY_7_1 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_0
CV_ENUM_RD_DWIDTH_1 DWIDTH_0
CV_ENUM_RD_PORT_INFO_1 USE_NO
CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0
CV_ENUM_USER_PRIORITY_1 PRIORITY_0
CV_ENUM_WR_DWIDTH_1 DWIDTH_0
CV_ENUM_WR_PORT_INFO_1 USE_NO
TG_TEMP_PORT_1 0
AV_PORT_2_CONNECT_TO_CV_PORT 2
CV_PORT_2_CONNECT_TO_AV_PORT 2
CV_AVL_DATA_WIDTH_PORT_2 0
CV_AVL_ADDR_WIDTH_PORT_2 0
CV_CPORT_TYPE_PORT_2 0
CV_AVL_NUM_SYMBOLS_PORT_2 2
CV_LSB_WFIFO_PORT_2 5
CV_MSB_WFIFO_PORT_2 5
CV_LSB_RFIFO_PORT_2 5
CV_MSB_RFIFO_PORT_2 5
CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED
CV_ENUM_CMD_PORT_IN_USE_2 FALSE
CV_ENUM_CPORT2_RFIFO_MAP FIFO_0
CV_ENUM_CPORT2_TYPE DISABLE
CV_ENUM_CPORT2_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_2 DISABLED
CV_ENUM_PORT2_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_2 WEIGHT_0
CV_ENUM_PRIORITY_1_2 WEIGHT_0
CV_ENUM_PRIORITY_2_2 WEIGHT_0
CV_ENUM_PRIORITY_3_2 WEIGHT_0
CV_ENUM_PRIORITY_4_2 WEIGHT_0
CV_ENUM_PRIORITY_5_2 WEIGHT_0
CV_ENUM_PRIORITY_6_2 WEIGHT_0
CV_ENUM_PRIORITY_7_2 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_0
CV_ENUM_RD_DWIDTH_2 DWIDTH_0
CV_ENUM_RD_PORT_INFO_2 USE_NO
CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0
CV_ENUM_USER_PRIORITY_2 PRIORITY_0
CV_ENUM_WR_DWIDTH_2 DWIDTH_0
CV_ENUM_WR_PORT_INFO_2 USE_NO
TG_TEMP_PORT_2 0
AV_PORT_3_CONNECT_TO_CV_PORT 3
CV_PORT_3_CONNECT_TO_AV_PORT 3
CV_AVL_DATA_WIDTH_PORT_3 0
CV_AVL_ADDR_WIDTH_PORT_3 0
CV_CPORT_TYPE_PORT_3 0
CV_AVL_NUM_SYMBOLS_PORT_3 2
CV_LSB_WFIFO_PORT_3 5
CV_MSB_WFIFO_PORT_3 5
CV_LSB_RFIFO_PORT_3 5
CV_MSB_RFIFO_PORT_3 5
CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED
CV_ENUM_CMD_PORT_IN_USE_3 FALSE
CV_ENUM_CPORT3_RFIFO_MAP FIFO_0
CV_ENUM_CPORT3_TYPE DISABLE
CV_ENUM_CPORT3_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_3 DISABLED
CV_ENUM_PORT3_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_3 WEIGHT_0
CV_ENUM_PRIORITY_1_3 WEIGHT_0
CV_ENUM_PRIORITY_2_3 WEIGHT_0
CV_ENUM_PRIORITY_3_3 WEIGHT_0
CV_ENUM_PRIORITY_4_3 WEIGHT_0
CV_ENUM_PRIORITY_5_3 WEIGHT_0
CV_ENUM_PRIORITY_6_3 WEIGHT_0
CV_ENUM_PRIORITY_7_3 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_0
CV_ENUM_RD_DWIDTH_3 DWIDTH_0
CV_ENUM_RD_PORT_INFO_3 USE_NO
CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0
CV_ENUM_USER_PRIORITY_3 PRIORITY_0
CV_ENUM_WR_DWIDTH_3 DWIDTH_0
CV_ENUM_WR_PORT_INFO_3 USE_NO
TG_TEMP_PORT_3 0
AV_PORT_4_CONNECT_TO_CV_PORT 4
CV_PORT_4_CONNECT_TO_AV_PORT 4
CV_AVL_DATA_WIDTH_PORT_4 0
CV_AVL_ADDR_WIDTH_PORT_4 0
CV_CPORT_TYPE_PORT_4 0
CV_AVL_NUM_SYMBOLS_PORT_4 2
CV_LSB_WFIFO_PORT_4 5
CV_MSB_WFIFO_PORT_4 5
CV_LSB_RFIFO_PORT_4 5
CV_MSB_RFIFO_PORT_4 5
CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED
CV_ENUM_CMD_PORT_IN_USE_4 FALSE
CV_ENUM_CPORT4_RFIFO_MAP FIFO_0
CV_ENUM_CPORT4_TYPE DISABLE
CV_ENUM_CPORT4_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_4 DISABLED
CV_ENUM_PORT4_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_4 WEIGHT_0
CV_ENUM_PRIORITY_1_4 WEIGHT_0
CV_ENUM_PRIORITY_2_4 WEIGHT_0
CV_ENUM_PRIORITY_3_4 WEIGHT_0
CV_ENUM_PRIORITY_4_4 WEIGHT_0
CV_ENUM_PRIORITY_5_4 WEIGHT_0
CV_ENUM_PRIORITY_6_4 WEIGHT_0
CV_ENUM_PRIORITY_7_4 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_0
CV_ENUM_RD_DWIDTH_4 DWIDTH_0
CV_ENUM_RD_PORT_INFO_4 USE_NO
CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0
CV_ENUM_USER_PRIORITY_4 PRIORITY_0
CV_ENUM_WR_DWIDTH_4 DWIDTH_0
CV_ENUM_WR_PORT_INFO_4 USE_NO
TG_TEMP_PORT_4 0
AV_PORT_5_CONNECT_TO_CV_PORT 5
CV_PORT_5_CONNECT_TO_AV_PORT 5
CV_AVL_DATA_WIDTH_PORT_5 0
CV_AVL_ADDR_WIDTH_PORT_5 0
CV_CPORT_TYPE_PORT_5 0
CV_AVL_NUM_SYMBOLS_PORT_5 2
CV_LSB_WFIFO_PORT_5 5
CV_MSB_WFIFO_PORT_5 5
CV_LSB_RFIFO_PORT_5 5
CV_MSB_RFIFO_PORT_5 5
CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED
CV_ENUM_CMD_PORT_IN_USE_5 FALSE
CV_ENUM_CPORT5_RFIFO_MAP FIFO_0
CV_ENUM_CPORT5_TYPE DISABLE
CV_ENUM_CPORT5_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_5 DISABLED
CV_ENUM_PORT5_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_5 WEIGHT_0
CV_ENUM_PRIORITY_1_5 WEIGHT_0
CV_ENUM_PRIORITY_2_5 WEIGHT_0
CV_ENUM_PRIORITY_3_5 WEIGHT_0
CV_ENUM_PRIORITY_4_5 WEIGHT_0
CV_ENUM_PRIORITY_5_5 WEIGHT_0
CV_ENUM_PRIORITY_6_5 WEIGHT_0
CV_ENUM_PRIORITY_7_5 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_0
CV_ENUM_RD_DWIDTH_5 DWIDTH_0
CV_ENUM_RD_PORT_INFO_5 USE_NO
CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0
CV_ENUM_USER_PRIORITY_5 PRIORITY_0
CV_ENUM_WR_DWIDTH_5 DWIDTH_0
CV_ENUM_WR_PORT_INFO_5 USE_NO
TG_TEMP_PORT_5 0
CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0
CV_INTG_RCFG_SUM_WT_PRIORITY_0 0
CV_INTG_SUM_WT_PRIORITY_0 0
CV_INTG_RCFG_SUM_WT_PRIORITY_1 0
CV_INTG_SUM_WT_PRIORITY_1 0
CV_INTG_RCFG_SUM_WT_PRIORITY_2 0
CV_INTG_SUM_WT_PRIORITY_2 0
CV_INTG_RCFG_SUM_WT_PRIORITY_3 0
CV_INTG_SUM_WT_PRIORITY_3 0
CV_INTG_RCFG_SUM_WT_PRIORITY_4 0
CV_INTG_SUM_WT_PRIORITY_4 0
CV_INTG_RCFG_SUM_WT_PRIORITY_5 0
CV_INTG_SUM_WT_PRIORITY_5 0
CV_INTG_RCFG_SUM_WT_PRIORITY_6 0
CV_INTG_SUM_WT_PRIORITY_6 0
CV_INTG_RCFG_SUM_WT_PRIORITY_7 0
CV_INTG_SUM_WT_PRIORITY_7 0
CONTINUE_AFTER_CAL_FAIL false
MAX10_CFG true
POWER_OF_TWO_BUS false
SOPC_COMPAT_RESET false
AVL_MAX_SIZE 4
BYTE_ENABLE true
ENABLE_CTRL_AVALON_INTERFACE true
CTL_DEEP_POWERDN_EN false
CTL_SELF_REFRESH_EN false
AUTO_POWERDN_EN false
AUTO_PD_CYCLES 0
CTL_USR_REFRESH_EN false
CTL_AUTOPCH_EN false
CTL_ZQCAL_EN false
ADDR_ORDER 0
CTL_LOOK_AHEAD_DEPTH 4
CONTROLLER_LATENCY 5
CFG_REORDER_DATA true
STARVE_LIMIT 10
CTL_CSR_ENABLED false
CTL_CSR_CONNECTION INTERNAL_JTAG
CTL_ECC_ENABLED false
CTL_HRB_ENABLED false
CTL_ECC_AUTO_CORRECTION_ENABLED false
MULTICAST_EN false
CTL_DYNAMIC_BANK_ALLOCATION false
CTL_DYNAMIC_BANK_NUM 4
DEBUG_MODE false
ENABLE_BURST_MERGE false
CTL_ENABLE_BURST_INTERRUPT false
CTL_ENABLE_BURST_TERMINATE false
LOCAL_ID_WIDTH 8
RDBUFFER_ADDR_WIDTH 7
WRBUFFER_ADDR_WIDTH 6
MAX_PENDING_WR_CMD 16
MAX_PENDING_RD_CMD 32
USE_MM_ADAPTOR true
USE_AXI_ADAPTOR false
HCX_COMPAT_MODE false
CTL_CMD_QUEUE_DEPTH 8
CTL_CSR_READ_ONLY 1
CFG_DATA_REORDERING_TYPE INTER_BANK
NUM_OF_PORTS 1
ENABLE_BONDING false
ENABLE_USER_ECC false
AVL_DATA_WIDTH_PORT 32,32,32,32,32,32
PRIORITY_PORT 1,1,1,1,1,1
WEIGHT_PORT 0,0,0,0,0,0
CPORT_TYPE_PORT Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
CORE_PERIPHERY_DUAL_CLOCK false
USE_DR_CLK false
DLL_USE_DR_CLK false
USE_2X_FF false
DUAL_WRITE_CLOCK false
GENERIC_PLL false
USE_HARD_READ_FIFO false
READ_FIFO_HALF_RATE true
PLL_MASTER true
DLL_MASTER true
PHY_VERSION_NUMBER 150
ENABLE_NIOS_OCI false
ENABLE_EMIT_JTAG_MASTER false
ENABLE_NIOS_JTAG_UART false
ENABLE_NIOS_PRINTF_OUTPUT false
ENABLE_LARGE_RW_MGR_DI_BUFFER false
ENABLE_EMIT_BFM_MASTER false
FORCE_SEQUENCER_TCL_DEBUG_MODE false
ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false
ENABLE_MAX_SIZE_SEQ_MEM false
MAKE_INTERNAL_NIOS_VISIBLE false
DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false
ENABLE_CSR_SOFT_RESET_REQ false
DUPLICATE_PLL_FOR_PHY_CLK false
MAX_LATENCY_COUNT_WIDTH 5
READ_VALID_FIFO_SIZE 16
EXTRA_VFIFO_SHIFT 0
TB_MEM_CLK_FREQ 300.0
TB_RATE HALF
TB_MEM_IF_DQ_WIDTH 8
TB_MEM_IF_READ_DQS_WIDTH 1
TB_PLL_DLL_MASTER true
FAST_SIM_CALIBRATION false
REF_CLK_FREQ 50.0
REF_CLK_FREQ_STR 50.0 MHz
REF_CLK_NS 20.0
REF_CLK_PS 20000.0
PLL_DR_CLK_FREQ 0.0
PLL_DR_CLK_FREQ_STR
PLL_DR_CLK_FREQ_SIM_STR 0 ps
PLL_DR_CLK_PHASE_PS 0
PLL_DR_CLK_PHASE_PS_STR
PLL_DR_CLK_PHASE_DEG 0.0
PLL_DR_CLK_PHASE_PS_SIM 0
PLL_DR_CLK_PHASE_PS_SIM_STR
PLL_DR_CLK_PHASE_DEG_SIM 0.0
PLL_DR_CLK_MULT 0
PLL_DR_CLK_DIV 0
PLL_MEM_CLK_FREQ 300.0
PLL_MEM_CLK_FREQ_STR 300.0 MHz
PLL_MEM_CLK_FREQ_SIM_STR 3334 ps
PLL_MEM_CLK_PHASE_PS 0
PLL_MEM_CLK_PHASE_PS_STR 0 ps
PLL_MEM_CLK_PHASE_DEG 0.0
PLL_MEM_CLK_PHASE_PS_SIM 0
PLL_MEM_CLK_PHASE_PS_SIM_STR 0 ps
PLL_MEM_CLK_PHASE_DEG_SIM 0.0
PLL_MEM_CLK_MULT 6
PLL_MEM_CLK_DIV 1
PLL_AFI_CLK_FREQ 150.0
PLL_AFI_CLK_FREQ_STR 150.0 MHz
PLL_AFI_CLK_FREQ_SIM_STR 6668 ps
PLL_AFI_CLK_PHASE_PS 0
PLL_AFI_CLK_PHASE_PS_STR 0 ps
PLL_AFI_CLK_PHASE_DEG 0.0
PLL_AFI_CLK_PHASE_PS_SIM 0
PLL_AFI_CLK_PHASE_PS_SIM_STR 0 ps
PLL_AFI_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_CLK_MULT 3
PLL_AFI_CLK_DIV 1
PLL_WRITE_CLK_FREQ 300.0
PLL_WRITE_CLK_FREQ_STR 300.0 MHz
PLL_WRITE_CLK_FREQ_SIM_STR 3334 ps
PLL_WRITE_CLK_PHASE_PS 2500
PLL_WRITE_CLK_PHASE_PS_STR 2500 ps
PLL_WRITE_CLK_PHASE_DEG 270.0
PLL_WRITE_CLK_PHASE_PS_SIM 2500
PLL_WRITE_CLK_PHASE_PS_SIM_STR 2500 ps
PLL_WRITE_CLK_PHASE_DEG_SIM 270.0
PLL_WRITE_CLK_MULT 6
PLL_WRITE_CLK_DIV 1
PLL_ADDR_CMD_CLK_FREQ 300.0
PLL_ADDR_CMD_CLK_FREQ_STR 300.0 MHz
PLL_ADDR_CMD_CLK_FREQ_SIM_STR 3334 ps
PLL_ADDR_CMD_CLK_PHASE_PS 0
PLL_ADDR_CMD_CLK_PHASE_PS_STR 0 ps
PLL_ADDR_CMD_CLK_PHASE_DEG 0.0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR 0 ps
PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 0.0
PLL_ADDR_CMD_CLK_MULT 6
PLL_ADDR_CMD_CLK_DIV 1
PLL_AFI_HALF_CLK_FREQ 300.0
PLL_AFI_HALF_CLK_FREQ_STR 300.0 MHz
PLL_AFI_HALF_CLK_FREQ_SIM_STR 3334 ps
PLL_AFI_HALF_CLK_PHASE_PS 2500
PLL_AFI_HALF_CLK_PHASE_PS_STR 2500 ps
PLL_AFI_HALF_CLK_PHASE_DEG 270.0
PLL_AFI_HALF_CLK_PHASE_PS_SIM 2500
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR 2500 ps
PLL_AFI_HALF_CLK_PHASE_DEG_SIM 270.0
PLL_AFI_HALF_CLK_MULT 6
PLL_AFI_HALF_CLK_DIV 1
PLL_NIOS_CLK_FREQ 0.0
PLL_NIOS_CLK_FREQ_STR
PLL_NIOS_CLK_FREQ_SIM_STR 0 ps
PLL_NIOS_CLK_PHASE_PS 0
PLL_NIOS_CLK_PHASE_PS_STR
PLL_NIOS_CLK_PHASE_DEG 0.0
PLL_NIOS_CLK_PHASE_PS_SIM 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR
PLL_NIOS_CLK_PHASE_DEG_SIM 0.0
PLL_NIOS_CLK_MULT 0
PLL_NIOS_CLK_DIV 0
PLL_CONFIG_CLK_FREQ 0.0
PLL_CONFIG_CLK_FREQ_STR
PLL_CONFIG_CLK_FREQ_SIM_STR 0 ps
PLL_CONFIG_CLK_PHASE_PS 0
PLL_CONFIG_CLK_PHASE_PS_STR
PLL_CONFIG_CLK_PHASE_DEG 0.0
PLL_CONFIG_CLK_PHASE_PS_SIM 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR
PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0
PLL_CONFIG_CLK_MULT 0
PLL_CONFIG_CLK_DIV 0
PLL_P2C_READ_CLK_FREQ 0.0
PLL_P2C_READ_CLK_FREQ_STR
PLL_P2C_READ_CLK_FREQ_SIM_STR 0 ps
PLL_P2C_READ_CLK_PHASE_PS 0
PLL_P2C_READ_CLK_PHASE_PS_STR
PLL_P2C_READ_CLK_PHASE_DEG 0.0
PLL_P2C_READ_CLK_PHASE_PS_SIM 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR
PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0
PLL_P2C_READ_CLK_MULT 0
PLL_P2C_READ_CLK_DIV 0
PLL_C2P_WRITE_CLK_FREQ 0.0
PLL_C2P_WRITE_CLK_FREQ_STR
PLL_C2P_WRITE_CLK_FREQ_SIM_STR 0 ps
PLL_C2P_WRITE_CLK_PHASE_PS 0
PLL_C2P_WRITE_CLK_PHASE_PS_STR
PLL_C2P_WRITE_CLK_PHASE_DEG 0.0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR
PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0
PLL_C2P_WRITE_CLK_MULT 0
PLL_C2P_WRITE_CLK_DIV 0
PLL_HR_CLK_FREQ 0.0
PLL_HR_CLK_FREQ_STR
PLL_HR_CLK_FREQ_SIM_STR 0 ps
PLL_HR_CLK_PHASE_PS 0
PLL_HR_CLK_PHASE_PS_STR
PLL_HR_CLK_PHASE_DEG 0.0
PLL_HR_CLK_PHASE_PS_SIM 0
PLL_HR_CLK_PHASE_PS_SIM_STR
PLL_HR_CLK_PHASE_DEG_SIM 0.0
PLL_HR_CLK_MULT 0
PLL_HR_CLK_DIV 0
PLL_AFI_PHY_CLK_FREQ 0.0
PLL_AFI_PHY_CLK_FREQ_STR
PLL_AFI_PHY_CLK_FREQ_SIM_STR 0 ps
PLL_AFI_PHY_CLK_PHASE_PS 0
PLL_AFI_PHY_CLK_PHASE_PS_STR
PLL_AFI_PHY_CLK_PHASE_DEG 0.0
PLL_AFI_PHY_CLK_PHASE_PS_SIM 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR
PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_PHY_CLK_MULT 0
PLL_AFI_PHY_CLK_DIV 0
REF_CLK_FREQ_CACHE_VALID true
REF_CLK_FREQ_PARAM_VALID false
REF_CLK_FREQ_MIN_PARAM 0.0
REF_CLK_FREQ_MAX_PARAM 0.0
REF_CLK_FREQ_MIN_CACHE 10.0
REF_CLK_FREQ_MAX_CACHE 500.0
PLL_DR_CLK_FREQ_PARAM 0.0
PLL_DR_CLK_FREQ_SIM_STR_PARAM
PLL_DR_CLK_PHASE_PS_PARAM 0
PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM
PLL_DR_CLK_MULT_PARAM 0
PLL_DR_CLK_DIV_PARAM 0
PLL_DR_CLK_FREQ_CACHE 0.0
PLL_DR_CLK_FREQ_SIM_STR_CACHE
PLL_DR_CLK_PHASE_PS_CACHE 0
PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE
PLL_DR_CLK_MULT_CACHE 0
PLL_DR_CLK_DIV_CACHE 0
PLL_MEM_CLK_FREQ_PARAM 0.0
PLL_MEM_CLK_FREQ_SIM_STR_PARAM
PLL_MEM_CLK_PHASE_PS_PARAM 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM
PLL_MEM_CLK_MULT_PARAM 0
PLL_MEM_CLK_DIV_PARAM 0
PLL_MEM_CLK_FREQ_CACHE 300.0
PLL_MEM_CLK_FREQ_SIM_STR_CACHE 3334 ps
PLL_MEM_CLK_PHASE_PS_CACHE 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_MEM_CLK_MULT_CACHE 6
PLL_MEM_CLK_DIV_CACHE 1
PLL_AFI_CLK_FREQ_PARAM 0.0
PLL_AFI_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_CLK_PHASE_PS_PARAM 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_CLK_MULT_PARAM 0
PLL_AFI_CLK_DIV_PARAM 0
PLL_AFI_CLK_FREQ_CACHE 150.0
PLL_AFI_CLK_FREQ_SIM_STR_CACHE 6668 ps
PLL_AFI_CLK_PHASE_PS_CACHE 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_AFI_CLK_MULT_CACHE 3
PLL_AFI_CLK_DIV_CACHE 1
PLL_WRITE_CLK_FREQ_PARAM 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_PARAM
PLL_WRITE_CLK_PHASE_PS_PARAM 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM
PLL_WRITE_CLK_MULT_PARAM 0
PLL_WRITE_CLK_DIV_PARAM 0
PLL_WRITE_CLK_FREQ_CACHE 300.0
PLL_WRITE_CLK_FREQ_SIM_STR_CACHE 3334 ps
PLL_WRITE_CLK_PHASE_PS_CACHE 2500
PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE 2500 ps
PLL_WRITE_CLK_MULT_CACHE 6
PLL_WRITE_CLK_DIV_CACHE 1
PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM
PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM
PLL_ADDR_CMD_CLK_MULT_PARAM 0
PLL_ADDR_CMD_CLK_DIV_PARAM 0
PLL_ADDR_CMD_CLK_FREQ_CACHE 300.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE 3334 ps
PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_ADDR_CMD_CLK_MULT_CACHE 6
PLL_ADDR_CMD_CLK_DIV_CACHE 1
PLL_AFI_HALF_CLK_FREQ_PARAM 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_HALF_CLK_MULT_PARAM 0
PLL_AFI_HALF_CLK_DIV_PARAM 0
PLL_AFI_HALF_CLK_FREQ_CACHE 300.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE 3334 ps
PLL_AFI_HALF_CLK_PHASE_PS_CACHE 2500
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE 2500 ps
PLL_AFI_HALF_CLK_MULT_CACHE 6
PLL_AFI_HALF_CLK_DIV_CACHE 1
PLL_NIOS_CLK_FREQ_PARAM 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_PARAM
PLL_NIOS_CLK_PHASE_PS_PARAM 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM
PLL_NIOS_CLK_MULT_PARAM 0
PLL_NIOS_CLK_DIV_PARAM 0
PLL_NIOS_CLK_FREQ_CACHE 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_CACHE
PLL_NIOS_CLK_PHASE_PS_CACHE 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE
PLL_NIOS_CLK_MULT_CACHE 0
PLL_NIOS_CLK_DIV_CACHE 0
PLL_CONFIG_CLK_FREQ_PARAM 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM
PLL_CONFIG_CLK_PHASE_PS_PARAM 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM
PLL_CONFIG_CLK_MULT_PARAM 0
PLL_CONFIG_CLK_DIV_PARAM 0
PLL_CONFIG_CLK_FREQ_CACHE 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE
PLL_CONFIG_CLK_PHASE_PS_CACHE 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE
PLL_CONFIG_CLK_MULT_CACHE 0
PLL_CONFIG_CLK_DIV_CACHE 0
PLL_P2C_READ_CLK_FREQ_PARAM 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM
PLL_P2C_READ_CLK_PHASE_PS_PARAM 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM
PLL_P2C_READ_CLK_MULT_PARAM 0
PLL_P2C_READ_CLK_DIV_PARAM 0
PLL_P2C_READ_CLK_FREQ_CACHE 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE
PLL_P2C_READ_CLK_PHASE_PS_CACHE 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE
PLL_P2C_READ_CLK_MULT_CACHE 0
PLL_P2C_READ_CLK_DIV_CACHE 0
PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM
PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM
PLL_C2P_WRITE_CLK_MULT_PARAM 0
PLL_C2P_WRITE_CLK_DIV_PARAM 0
PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE
PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE
PLL_C2P_WRITE_CLK_MULT_CACHE 0
PLL_C2P_WRITE_CLK_DIV_CACHE 0
PLL_HR_CLK_FREQ_PARAM 0.0
PLL_HR_CLK_FREQ_SIM_STR_PARAM
PLL_HR_CLK_PHASE_PS_PARAM 0
PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM
PLL_HR_CLK_MULT_PARAM 0
PLL_HR_CLK_DIV_PARAM 0
PLL_HR_CLK_FREQ_CACHE 0.0
PLL_HR_CLK_FREQ_SIM_STR_CACHE
PLL_HR_CLK_PHASE_PS_CACHE 0
PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE
PLL_HR_CLK_MULT_CACHE 0
PLL_HR_CLK_DIV_CACHE 0
PLL_AFI_PHY_CLK_FREQ_PARAM 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_PHY_CLK_MULT_PARAM 0
PLL_AFI_PHY_CLK_DIV_PARAM 0
PLL_AFI_PHY_CLK_FREQ_CACHE 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE
PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE
PLL_AFI_PHY_CLK_MULT_CACHE 0
PLL_AFI_PHY_CLK_DIV_CACHE 0
SPEED_GRADE_CACHE 6
IS_ES_DEVICE_CACHE false
MEM_CLK_FREQ_CACHE 300.0
REF_CLK_FREQ_CACHE 50.0
RATE_CACHE Half
HCX_COMPAT_MODE_CACHE false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE MAX10
COMMAND_PHASE_CACHE 0.0
MEM_CK_PHASE_CACHE 0.0
P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0
C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0
ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0
SEQUENCER_TYPE_CACHE NIOS
USE_MEM_CLK_FREQ_CACHE false
PLL_CLK_CACHE_VALID true
PLL_CLK_PARAM_VALID false
ENABLE_EXTRA_REPORTING false
NUM_EXTRA_REPORT_PATH 10
ENABLE_ISS_PROBES false
CALIB_REG_WIDTH 8
USE_SEQUENCER_BFM false
PLL_SHARING_MODE None
NUM_PLL_SHARING_INTERFACES 1
EXPORT_AFI_HALF_CLK false
ABSTRACT_REAL_COMPARE_TEST false
INCLUDE_BOARD_DELAY_MODEL false
INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false
USE_FAKE_PHY_INTERNAL false
USE_FAKE_PHY false
FORCE_MAX_LATENCY_COUNT_WIDTH 0
USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false
ENABLE_NON_DESTRUCTIVE_CALIB false
USE_USER_RDIMM_VALUE false
ENABLE_DELAY_CHAIN_WRITE false
TRACKING_ERROR_TEST false
TRACKING_WATCH_TEST false
MARGIN_VARIATION_TEST false
AC_ROM_USER_ADD_0 0_0000_0000_0000
AC_ROM_USER_ADD_1 0_0000_0000_1000
TREFI 35100
REFRESH_INTERVAL 15000
ENABLE_NON_DES_CAL_TEST false
TRFC 350
ENABLE_NON_DES_CAL false
EXTRA_SETTINGS
MEM_DEVICE MISSING_MODEL
FORCE_SYNTHESIS_LANGUAGE
NUM_SUBGROUP_PER_READ_DQS 1
QVLD_EXTRA_FLOP_STAGES 0
QVLD_WR_ADDRESS_OFFSET 4
MAX_WRITE_LATENCY_COUNT_WIDTH 4
NUM_WRITE_PATH_FLOP_STAGES 1
NUM_AC_FR_CYCLE_SHIFTS 0
FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0
NUM_WRITE_FR_CYCLE_SHIFTS 1
PERFORM_READ_AFTER_WRITE_CALIBRATION false
SEQ_BURST_COUNT_WIDTH 1
VCALIB_COUNT_WIDTH 2
PLL_PHASE_COUNTER_WIDTH 4
DQS_DELAY_CHAIN_PHASE_SETTING 2
DQS_PHASE_SHIFT 9000
DELAYED_CLOCK_PHASE_SETTING 2
IO_DQS_IN_RESERVE 3
IO_DQS_OUT_RESERVE 3
IO_DQ_OUT_RESERVE 0
IO_DM_OUT_RESERVE 0
IO_DQS_EN_DELAY_OFFSET 0
IO_DQS_EN_PHASE_MAX 7
IO_DQDQS_OUT_PHASE_MAX 14
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false
MEM_CLK_NS 3.333
MEM_CLK_PS 3333.0
CALIB_LFIFO_OFFSET 4
CALIB_VFIFO_OFFSET 12
DELAY_PER_OPA_TAP 416
DELAY_PER_DCHAIN_TAP 50
DELAY_PER_DQS_EN_DCHAIN_TAP 50
DQS_EN_DELAY_MAX 7
DQS_IN_DELAY_MAX 15
IO_IN_DELAY_MAX 15
IO_OUT1_DELAY_MAX 15
IO_OUT2_DELAY_MAX 7
IO_STANDARD SSTL-15
VFIFO_AS_SHIFT_REG true
SEQUENCER_TYPE NIOS
NIOS_HEX_FILE_LOCATION ../
ADVERTIZE_SEQUENCER_SW_BUILD_FILES false
NEGATIVE_WRITE_CK_PHASE true
MEM_T_WL 5
MEM_T_RL 5
PHY_CLKBUF false
USE_LDC_AS_LOW_SKEW_CLOCK false
USE_LDC_FOR_ADDR_CMD false
ENABLE_LDC_MEM_CK_ADJUSTMENT false
MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0
LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true
LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0
FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false
NON_LDC_ADDR_CMD_MEM_CK_INVERT false
REGISTER_C2P false
EARLY_ADDR_CMD_CLK_TRANSFER false
MAX10_RTL_SEQ true
PHY_ONLY false
SEQ_MODE 0
ADVANCED_CK_PHASES false
COMMAND_PHASE 0.0
MEM_CK_PHASE 0.0
P2C_READ_CLOCK_ADD_PHASE 0.0
C2P_WRITE_CLOCK_ADD_PHASE 0.0
ACV_PHY_CLK_ADD_FR_PHASE 0.0
MEM_VOLTAGE 1.5V DDR3
PLL_LOCATION Top_Bottom
SKIP_MEM_INIT true
READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS
DQ_INPUT_REG_USE_CLKN false
DQS_DQSN_MODE DIFFERENTIAL
AFI_DEBUG_INFO_WIDTH 32
CALIBRATION_MODE Skip
NIOS_ROM_DATA_WIDTH 32
NIOS_ROM_ADDRESS_WIDTH 13
READ_FIFO_SIZE 8
PHY_CSR_ENABLED false
PHY_CSR_CONNECTION INTERNAL_JTAG
USER_DEBUG_LEVEL 1
TIMING_BOARD_DERATE_METHOD AUTO
TIMING_BOARD_CK_CKN_SLEW_RATE 2.0
TIMING_BOARD_AC_SLEW_RATE 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0
TIMING_BOARD_DQ_SLEW_RATE 1.0
TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0
TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0
TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0
TIMING_BOARD_TIS 0.0
TIMING_BOARD_TIH 0.0
TIMING_BOARD_TDS 0.0
TIMING_BOARD_TDH 0.0
TIMING_BOARD_TIS_APPLIED 0.32
TIMING_BOARD_TIH_APPLIED 0.22
TIMING_BOARD_TDS_APPLIED 0.16
TIMING_BOARD_TDH_APPLIED 0.145
TIMING_BOARD_ISI_METHOD AUTO
TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H 0.0
TIMING_BOARD_DQ_EYE_REDUCTION 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0
TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0
TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0
PACKAGE_DESKEW false
AC_PACKAGE_DESKEW false
TIMING_BOARD_MAX_CK_DELAY 0.2443
TIMING_BOARD_MAX_DQS_DELAY 0.21929
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.02286
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.02286
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.04429
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.04429
TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05
TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0
TIMING_BOARD_SKEW_WITHIN_DQS 0.01806
TIMING_BOARD_SKEW_BETWEEN_DQS 0.04246
TIMING_BOARD_DQ_TO_DQS_SKEW -0.01152
TIMING_BOARD_AC_SKEW 0.07801
TIMING_BOARD_AC_TO_CK_SKEW -0.04709
ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false
CORE_DEBUG_CONNECTION EXPORT
ADD_EXTERNAL_SEQ_DEBUG_NIOS false
ED_EXPORT_SEQ_DEBUG false
ADD_EFFICIENCY_MONITOR false
ENABLE_ABS_RAM_MEM_INIT false
ENABLE_ABS_RAM_INTERNAL false
ENABLE_ABSTRACT_RAM false
ABS_RAM_MEM_INIT_FILENAME meminit
DLL_DELAY_CTRL_WIDTH 6
DLL_OFFSET_CTRL_WIDTH 6
DELAY_BUFFER_MODE HIGH
DELAY_CHAIN_LENGTH 8
DLL_SHARING_MODE None
NUM_DLL_SHARING_INTERFACES 1
OCT_TERM_CONTROL_WIDTH 14
OCT_SHARING_MODE None
NUM_OCT_SHARING_INTERFACES 1
AUTO_DEVICE 10M50DAF484C6GES
AUTO_DEVICE_SPEEDGRADE 6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mem_resetn

altera_reset_bridge v15.0


Parameters

ACTIVE_LOW_RESET 1
SYNCHRONOUS_EDGES none
NUM_RESET_OUTPUTS 1
USE_RESET_REQUEST 0
AUTO_CLK_CLOCK_RATE -1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

onchip_ram

altera_avalon_onchip_memory2 v15.0
cpu data_master   onchip_ram
  s1
debug_reset_request  
  reset1
sys_clk clk  
  clk1
clk_reset  
  reset1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName onchip_mem.hex
instanceID NONE
memorySize 2048
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
copyInitFile false
useShallowMemBlocks false
writable true
ecc_enabled false
resetrequest_enabled true
autoInitializationFileName q_sys_onchip_ram
deviceFamily MAX10FPGA
deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width 9
derived_set_data_width 32
derived_gui_ram_block_type Automatic
derived_is_hardcopy false
derived_init_file_name q_sys_onchip_ram.hex
generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE q_sys_onchip_ram
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 2048
WRITABLE 1

sgdma_rx

altera_avalon_sgdma v15.0
cpu data_master   sgdma_rx
  csr
irq  
  csr_irq
debug_reset_request  
  reset
eth_tse receive  
  in
sys_clk clk  
  clk
clk_reset  
  reset
descriptor_read   descriptor_memory
  s1
descriptor_write  
  s1
m_write   mem_if_ddr3_emif_0
  avl


Parameters

addressWidth 32
alwaysDoMaxBurst true
avalonMMByteReorderMode 0
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 32
readBurstcountWidth 4
sinkErrorWidth 6
sourceErrorWidth 0
transferMode STREAM_TO_MEMORY
writeBurstcountWidth 4
deviceFamilyString MAX10FPGA
actualDataTransferFIFODepth 64
commandFIFODataWidth 104
symbolsPerBeat 4
byteEnableWidth 4
emptyWidth 2
hasReadBlock false
hasWriteBlock true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ADDRESS_WIDTH 32
ALWAYS_DO_MAX_BURST 1
ATLANTIC_CHANNEL_DATA_WIDTH 4
AVALON_MM_BYTE_REORDER_MODE 0
BURST_DATA_WIDTH 8
BURST_TRANSFER 0
BYTES_TO_TRANSFER_DATA_WIDTH 16
CHAIN_WRITEBACK_DATA_WIDTH 32
COMMAND_FIFO_DATA_WIDTH 104
CONTROL_DATA_WIDTH 8
CONTROL_SLAVE_ADDRESS_WIDTH 4
CONTROL_SLAVE_DATA_WIDTH 32
DESCRIPTOR_READ_BURST 0
DESC_DATA_WIDTH 32
HAS_READ_BLOCK 0
HAS_WRITE_BLOCK 1
IN_ERROR_WIDTH 6
OUT_ERROR_WIDTH 0
READ_BLOCK_DATA_WIDTH 32
READ_BURSTCOUNT_WIDTH 4
STATUS_TOKEN_DATA_WIDTH 24
STREAM_DATA_WIDTH 32
SYMBOLS_PER_BEAT 4
UNALIGNED_TRANSFER 0
WRITE_BLOCK_DATA_WIDTH 32
WRITE_BURSTCOUNT_WIDTH 4

sgdma_tx

altera_avalon_sgdma v15.0
cpu data_master   sgdma_tx
  csr
irq  
  csr_irq
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset
descriptor_read   descriptor_memory
  s1
descriptor_write  
  s1
m_read   mem_if_ddr3_emif_0
  avl
out   eth_tse
  transmit


Parameters

addressWidth 32
alwaysDoMaxBurst true
avalonMMByteReorderMode 0
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 32
readBurstcountWidth 4
sinkErrorWidth 0
sourceErrorWidth 1
transferMode MEMORY_TO_STREAM
writeBurstcountWidth 4
deviceFamilyString MAX10FPGA
actualDataTransferFIFODepth 64
commandFIFODataWidth 104
symbolsPerBeat 4
byteEnableWidth 4
emptyWidth 2
hasReadBlock true
hasWriteBlock false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ADDRESS_WIDTH 32
ALWAYS_DO_MAX_BURST 1
ATLANTIC_CHANNEL_DATA_WIDTH 4
AVALON_MM_BYTE_REORDER_MODE 0
BURST_DATA_WIDTH 8
BURST_TRANSFER 0
BYTES_TO_TRANSFER_DATA_WIDTH 16
CHAIN_WRITEBACK_DATA_WIDTH 32
COMMAND_FIFO_DATA_WIDTH 104
CONTROL_DATA_WIDTH 8
CONTROL_SLAVE_ADDRESS_WIDTH 4
CONTROL_SLAVE_DATA_WIDTH 32
DESCRIPTOR_READ_BURST 0
DESC_DATA_WIDTH 32
HAS_READ_BLOCK 1
HAS_WRITE_BLOCK 0
IN_ERROR_WIDTH 0
OUT_ERROR_WIDTH 1
READ_BLOCK_DATA_WIDTH 32
READ_BURSTCOUNT_WIDTH 4
STATUS_TOKEN_DATA_WIDTH 24
STREAM_DATA_WIDTH 32
SYMBOLS_PER_BEAT 4
UNALIGNED_TRANSFER 0
WRITE_BLOCK_DATA_WIDTH 32
WRITE_BURSTCOUNT_WIDTH 4

sys_clk

clock_source v15.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

sys_clk_timer

altera_avalon_timer v15.0
cpu data_master   sys_clk_timer
  s1
irq  
  irq
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 10
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 50000000
watchdogPulse 2
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0
loadValue 499999
mult 0
ticksPerSec 100
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 499999
MULT 0.001
PERIOD 10
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 100
TIMEOUT_PULSE_OUTPUT 0

sysid

altera_avalon_sysid_qsys v15.0
cpu data_master   sysid
  control_slave
debug_reset_request  
  reset
sys_clk clk  
  clk
clk_reset  
  reset


Parameters

id -87110914
timestamp 1427286953
AUTO_DEVICE_FAMILY MAX10FPGA
deviceFamily MAX 10
generateLegacySim false
  

Software Assignments

ID 4207856382
TIMESTAMP 1427286953
generation took 0.01 seconds rendering took 0.19 seconds