ctrlcfg3

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA034

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_rld3_multibank_mode

0x0

cfg_geardn_en

0x0

cfg_open_page_en

0x0

cfg_arbiter_type

0x0

cfg_dbc3_dualport_en

0x0

cfg_dbc2_dualport_en

0x0

cfg_dbc1_dualport_en

0x0

cfg_dbc0_dualport_en

0x0

cfg_ctrl_dualport_en

0x0

cfg_dbc3_in_protocol

0x0

cfg_dbc2_in_protocol

0x0

cfg_dbc1_in_protocol

0x0

cfg_dbc0_in_protocol

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_ctrl_in_protocol

0x0

cfg_dbc3_cmd_rate

0x0

cfg_dbc2_cmd_rate

0x0

cfg_dbc1_cmd_rate

0x0

cfg_dbc0_cmd_rate

0x0

cfg_ctrl_cmd_rate

0x0

ctrlcfg3 Fields

Bit Name Description Access Reset
30:28 cfg_rld3_multibank_mode
Multibank setting, specific for RLDRAM3. Set this to: - 3
RW 0x0
27 cfg_geardn_en
Set to 1 to enable the gear down mode for DDR4
RW 0x0
26 cfg_open_page_en
Set to 1 to enable the open page policy when command reordering is disabled (cfg_cmd_reorder = 0). This bit does not matter when cfg_cmd_reorder is 1.
RW 0x0
25 cfg_arbiter_type
Indicates controller arbiter operating mode. Set this to: - 1
RW 0x0
24 cfg_dbc3_dualport_en
Enable the second data port for RLDRAM3 only (BL=2 or 4)
RW 0x0
23 cfg_dbc2_dualport_en
Enable the second data port for RLDRAM3 only (BL=2 or 4)
RW 0x0
22 cfg_dbc1_dualport_en
Enable the second data port for RLDRAM3 only (BL=2 or 4)
RW 0x0
21 cfg_dbc0_dualport_en
Enable the second data port for RLDRAM3 only (BL=2 or 4)
RW 0x0
20 cfg_ctrl_dualport_en
Enable the second command port for RLDRAM3 only (BL=2 or 4)
RW 0x0
19 cfg_dbc3_in_protocol
1
RW 0x0
18 cfg_dbc2_in_protocol
1
RW 0x0
17 cfg_dbc1_in_protocol
1
RW 0x0
16 cfg_dbc0_in_protocol
1
RW 0x0
15 cfg_ctrl_in_protocol
1
RW 0x0
14:12 cfg_dbc3_cmd_rate
3
RW 0x0
11:9 cfg_dbc2_cmd_rate
3
RW 0x0
8:6 cfg_dbc1_cmd_rate
3
RW 0x0
5:3 cfg_dbc0_cmd_rate
3
RW 0x0
2:0 cfg_ctrl_cmd_rate
3
RW 0x0