Controls the L3 master HPROT AHB-Lite signal.
These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation
All fields are reset by a cold or warm reset.
Module Instance | Base Address | Register Address |
---|---|---|
i_sys_mgr_core | 0xFFD06000 | 0xFFD06038 |
Offset: 0x38
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
hprot RW 0x1 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
3:0 | hprot | Defines HPROT[4:1]. HPROT[0] from usb is tied HIGH allow only data access. ========================== HPROT[4] Allocate 0: L3 master accesses for the module are non-allocatable 1: L3 master accesses for the module are allocatable ========================== HPROT[3] Cachable 0: L3 master accesses for the module are non-cacheable. 1: L3 master accesses for the module are cacheable. ========================== HPROT[2] Bufferable 0: L3 master accesses for the module are not bufferable. 1: L3 master accesses for the module are bufferable. ========================== HPROT[1] Privileged 0: L3 master accesses for the module are not privileged. 1: L3 master accesses for the module are privileged. ========================== |
RW | 0x1 |