This write one to clear register indicates that the DCLKCNT has counted down to zero. The DCLKCNT is used by software to drive spurious DCLKs to the FPGA. Software will poll this bit after writing DCLKCNT to know when all of the DCLKs have been sent.
Module Instance | Base Address | Register Address |
---|---|---|
i_fpga_mgr_fpgamgrregs | 0xFFD03000 | 0xFFD0300C |
Offset: 0xC
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
dcntdone RW 0x0 |
Bit | Name | Description | Access | Reset | ||||||
---|---|---|---|---|---|---|---|---|---|---|
0 | dcntdone | This bit is write one to clear. This bit gets set after the DCLKCNT has counted down to zero (transition from 1 to 0).
|
RW | 0x0 |