Module Instance | Base Address | Register Address |
---|---|---|
i_io48_hmc_mmr_io48_mmr | 0xFFCFA000 | 0xFFCFA02C |
Offset: 0x2C
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
cfg_dbc3_enable_dm 0x0 |
cfg_dbc2_enable_dm 0x0 |
cfg_dbc1_enable_dm 0x0 |
cfg_dbc0_enable_dm 0x0 |
cfg_ctrl_enable_dm 0x0 |
cfg_dqstrk_en 0x0 |
cfg_starve_limit 0x0 |
cfg_reorder_read 0x0 |
cfg_dbc3_reorder_rdata 0x0 |
cfg_dbc2_reorder_rdata 0x0 |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
cfg_dbc1_reorder_rdata 0x0 |
cfg_dbc0_reorder_rdata 0x0 |
cfg_ctrl_reorder_rdata 0x0 |
cfg_reorder_data 0x0 |
cfg_dbc3_enable_ecc 0x0 |
cfg_dbc2_enable_ecc 0x0 |
cfg_dbc1_enable_ecc 0x0 |
cfg_dbc0_enable_ecc 0x0 |
cfg_ctrl_enable_ecc 0x0 |
cfg_addr_order 0x0 |
cfg_dbc3_burst_length 0x0 |
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
30 | cfg_dbc3_enable_dm | Set to a one to enable DRAM operation if DM pins are connected. |
RW | 0x0 |
29 | cfg_dbc2_enable_dm | Set to a one to enable DRAM operation if DM pins are connected. |
RW | 0x0 |
28 | cfg_dbc1_enable_dm | Set to a one to enable DRAM operation if DM pins are connected. |
RW | 0x0 |
27 | cfg_dbc0_enable_dm | Set to a one to enable DRAM operation if DM pins are connected. |
RW | 0x0 |
26 | cfg_ctrl_enable_dm | Set to a one to enable DRAM operation if DM pins are connected. |
RW | 0x0 |
25 | cfg_dqstrk_en | Enables DQS tracking in the PHY. |
RW | 0x0 |
24:19 | cfg_starve_limit | Specifies the number of DRAM burst transactions an individual transaction will allow to reorder ahead of it before its priority is raised in the memory controller. |
RW | 0x0 |
18 | cfg_reorder_read | This bit controls whether the controller can re-order read command to. 1 |
RW | 0x0 |
17 | cfg_dbc3_reorder_rdata | This bit controls whether the controller need to re-order the read return data. |
RW | 0x0 |
16 | cfg_dbc2_reorder_rdata | This bit controls whether the controller need to re-order the read return data. |
RW | 0x0 |
15 | cfg_dbc1_reorder_rdata | This bit controls whether the controller need to re-order the read return data. |
RW | 0x0 |
14 | cfg_dbc0_reorder_rdata | This bit controls whether the controller need to re-order the read return data. |
RW | 0x0 |
13 | cfg_ctrl_reorder_rdata | This bit controls whether the controller need to re-order the read return data. |
RW | 0x0 |
12 | cfg_reorder_data | This bit controls whether the controller can re-order operations to optimize SDRAM bandwidth. It should generally be set to a one. |
RW | 0x0 |
11 | cfg_dbc3_enable_ecc | Enable the generation and checking of ECC. |
RW | 0x0 |
10 | cfg_dbc2_enable_ecc | Enable the generation and checking of ECC. |
RW | 0x0 |
9 | cfg_dbc1_enable_ecc | Enable the generation and checking of ECC. |
RW | 0x0 |
8 | cfg_dbc0_enable_ecc | Enable the generation and checking of ECC. |
RW | 0x0 |
7 | cfg_ctrl_enable_ecc | Enable the generation and checking of ECC. |
RW | 0x0 |
6:5 | cfg_addr_order | Selects the order for address interleaving. Programming this field with different values gives different mappings between the AXI or Avalon-MM address and the SDRAM address. Program this field with the following binary values to select the ordering. "00" - chip, row, bank(BG, BA), column; "01" - chip, bank(BG, BA), row, column; "10"-row, chip, bank(BG, BA), column; |
RW | 0x0 |
4:0 | cfg_dbc3_burst_length | Configures burst length for DBC3. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3 abd DDR4, this should be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with 2 or 4 or 8 |
RW | 0x0 |