caltiming0

         
      
Module Instance Base Address Register Address
i_io48_hmc_mmr_io48_mmr 0xFFCFA000 0xFFCFA07C

Offset: 0x7C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_act_to_act_diff_bg

0x0

cfg_t_param_act_to_act_diff_bank

0x0

cfg_t_param_act_to_act

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_act_to_act

0x0

cfg_t_param_act_to_pch

0x0

cfg_t_param_act_to_rdwr

0x0

caltiming0 Fields

Bit Name Description Access Reset
29:24 cfg_t_param_act_to_act_diff_bg
Active to activate timing on different bank groups, DDR4 only
RW 0x0
23:18 cfg_t_param_act_to_act_diff_bank
Active to activate timing on different banks, for DDR4 same bank group
RW 0x0
17:12 cfg_t_param_act_to_act
Active to activate timing on same bank
RW 0x0
11:6 cfg_t_param_act_to_pch
Active to precharge
RW 0x0
5:0 cfg_t_param_act_to_rdwr
Activate to Read/write command timing
RW 0x0