Paper: 32nm Logic Technology for High Performance Microprocessors

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Paper: 32nm Logic Technology for High Performance Microprocessors

High Performance 32-nm Logic Technology Featuring 2nd Generation High-k + Metal Gate Transistors

Abstract: A 32-nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32-nm or 28-nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um Ioff. PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported. Technology Overview: Continuing Moore’s law to the 32-nm technology node requires difficult trade-offs in gate length, S/D contact area and contact-to-gate margins. As dimensions are reduced, less area is available for contacting S/D regions leading to potential Rext increases as well as less area for introducing strain for mobility enhancement to improve device performance. To continue the historical trends of both area and performance improvement requires novel solutions. Figure 1 shows the 32-nm node is continuing the historic trend in gate pitch.

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