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Enhanced MCA Logging in Future Intel® Xeon® Processors

White Paper: Provides usage models, software flows, and reporting mechanisms for enhanced MCA logging and I/O MCA in future Intel® Xeon® processors.

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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI CPU I/O Protocol Specification v0.9

Covers core code and services required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI.

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Intel® Itanium® Architecture Software Developer’s Manual Specification Update

Specification update: documentation errata, specification clarifications, changes to Intel® Itanium® Architecture Software Developer’s Manual.

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Architecture Intel® Many Integrated Core (MIC) avancée

L'architecture Intel® Many Integrated Core (Intel® MIC) marque un pas de géant en matière de vitesse, de performances et de compatibilité des supercalculateurs.

Intel® Xeon Phi™ Coprocessor: Software Developers Guide

Software Developers Guide: Intel® Xeon Phi™ coprocessor architecture, power management, RAS features, OS support, APIs, usage models, more.

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EMC Improves Efficiency with Development and Testing in the Cloud

Case Study: Development and testing in the cloud with Intel® Xeon® processor E5 v2 family helps EMC improve efficiency of storage solutions.

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Ressources logicielles pour les processeurs Intel® Itanium®

Ressources logicielles pour les processeurs Intel® Itanium®

Jefferson Lab Improves Application Performance Case Study

Jefferson Lab improves scientific application performance for faster results with Intel® Xeon Phi™ coprocessor-based Seneca servers and Linux* OS.

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Intel® 7500 Scalable Memory Buffer Specification Update

This document contains updates to Intel® 7500 Scalable Memory Buffer. It is a compilation of device and documentation clarifications and changes.

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