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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI CPU I/O Protocol Specification v0.9

Covers core code and services required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI.

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Intel® 7500 Scalable Memory Buffer Datasheet

Datasheet: Intel® 7500 Scalable Memory Buffer Datasheet.

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Intel E8870 Scalable Node Controller (SNC) Datasheet

Intel® E8870 chipset supports up to four processors, and up to eight processors with the Scalability Port Switch component.

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Migrating from SPARC* to HP and Intel® Standards-based Infrastructure

White Paper: Outlines HP Converged Infrastructure* benefits, design alternatives, infrastructure planning, and migration process recommendations.

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Dual-Core Intel® Itanium® 2 Processor: Reference Manual Update

Reference manual for the Dual-Core Intel® Itanium® 2 processor on software development and optimization.

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EFI Human Interface Infrastructure Specification v0.91

Defines core code for implementation of Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.92

Defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI Status Codes Specification v0.92

Updated: Defines the basic components, status code classes, and status code architecture required for Intel® Platform Innovation Framework for EFI.

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Intel® Itanium® Processor 9000 and 9100 Series Datasheet

Intel® Itanium® processor 9000 and 9100 series.

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