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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI CPU I/O Protocol Specification v0.9

Covers core code and services required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.91

Defines core code for implementation of Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.92

Defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI Status Codes Specification v0.92

Updated: Defines the basic components, status code classes, and status code architecture required for Intel® Platform Innovation Framework for EFI.

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Intel® Itanium® Architecture Software Developer’s Manual Specification Update

Specification update: documentation errata, specification clarifications, changes to Intel® Itanium® Architecture Software Developer’s Manual.

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Architecture Intel® Many Integrated Core (MIC) avancée

L'architecture Intel® Many Integrated Core (Intel® MIC) marque un pas de géant en matière de vitesse, de performances et de compatibilité des supercalculateurs.

Intel® Xeon Phi™ Coprocessor: Software Developers Guide

Software Developers Guide: Intel® Xeon Phi™ coprocessor architecture, power management, RAS features, OS support, APIs, usage models, more.

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EMC Improves Efficiency with Development and Testing in the Cloud

Case Study: Development and testing in the cloud with Intel® Xeon® processor E5 v2 family helps EMC improve efficiency of storage solutions.

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Intel® Itanium® Processor 9500 Series: Reference Manual

Software development and optimization guide for the Intel® Itanium® processor 9500 series with microarchitectural description and performance info.