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PHY Interface for PCI Express*, SATA, and USB Specification V4.3

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PHY Interface for PCI Express*, SATA, and USB Specification V4.3

Introduction
The PHY Interface for the PCI Express* (PIPE), SATA, and USB architectures is intended to enable the development of functionally equivalent PCI Express, SATA, and USB PHYs. Such PHYs can be delivered as discrete ICs or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE-compliant PHY, and it defines a standard interface between such a PHY and a media access control (MAC) layer and link layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible, the PIPE specification references the PCI Express base specification, SATA 3.0 specification, or USB 3.1 specification rather than repeating its content. In case of conflicts, the PCI-Express Base specification, SATA 3.0 specification, and USB 3.1 specification shall supersede the PIPE specification.

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